G1-300B-85-2.0
| Model | G1-300B-85-2.0 |
| Description | Processor Series Low Power Integrated x86 Solution |
| PDF file | Total 247 pages (File size: 4M) |
| Chip Manufacturer | NSC |
Geode™ GX1 Processor Series
Integrated Functions
(Continued)
Table 4-15. Memory Controller Registers (Continued)
Bit
10:8
Name
RRD
Description
ACT(0) to ACT(1) Command Period (tRRD):
Minimum number of SDRAM clocks between ACT and
ACT command to two different component banks within the same module bank. The memory controller
does not perform back-to-back Activate commands to two different component banks without a READ
or WRITE command between them. Hence, this field should be set to 001.
Reserved:
Set to 0.
Data-in to PRE command period (tDPL):
Minimum number of SDRAM clocks from the time the last
write datum is sampled till the bank is precharged:
000 = Reserved
001 = 1 CLK
3:0
Note:
RSVD
010 = 2 CLK
011 = 3 CLK
100 = 4 CLK
101 = 5 CLK
110 = 6 CLK
111 = 7 CLK
7
6:4
RSVD
DPL
Reserved:
Leave unchanged. Always returns a 101h.
Refer to the SDRAM manufacturer’s specification for more information on component banks.
MC_GBASE_ADD (R/W)
Reserved:
Set to 0.
Test Enable TEST[3:0]:
0 = TEST[3:0] are driven low (normal operation)
1 = TEST[3:0] pins are used to output test information
Test Enable Shared Control Pins:
0 = RASB#, CASB#, CKEB, WEB# (normal operation)
1 = RASB#, CASB#, CKEB, WEB# are used to output test information
Select:
This field is used for debug purposes only. Should be left at zero for normal operation.
Reserved:
Set to 0.
Graphics Base Address:
This field indicates the graphics memory base address, which is program-
mable on 512 KB boundaries. This field corresponds to address bits [29:19].
Note that BC_DRAM_TOP must be set to a value lower than the Graphics Base Address.
Default Value = 00000000h
GX_BASE+8414h-8417h
31:18
17
RSVD
TE
16
TECTL
15:12
11
10:0
SEL
RSVD
GBADD
GX_BASE+8418h-841Bh
31:10
9:0
RSVD
DRADD
Reserved:
Set to 0.
MC_DR_ADD (R/W)
Default Value = 00000000h
Dirty RAM Address:
This field is the address index that is used to access the Dirty RAM with the
MC_DR_ACC register. This field does not auto increment.
MC_DR_ACC (R/W)
Reserved:
Set to 0.
Dirty Bit:
This bit is read/write accessible.
Valid Bit:
This bit is read/write accessible.
Default Value = 0000000xh
GX_BASE+841Ch-841Fh
31:2
1
0
RSVD
D
V
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