G1-300B-85-2.0
| Model | G1-300B-85-2.0 |
| Description | Processor Series Low Power Integrated x86 Solution |
| PDF file | Total 247 pages (File size: 4M) |
| Chip Manufacturer | NSC |
Geode™ GX1 Processor Series
Processor Programming
(Continued)
Table 3-15. TR7-TR6 Bit Definitions
Bit
TR7 Register
31:12
Physical
Address
Physical Address:
TLB lookup: Data field from the TLB.
TLB write: Data field written into the TLB.
11:10
9:7
RSVD
TLB LRU
Reserved:
Set to 0.
LRU Bits:
TLB lookup: LRU bits associated with the TLB entry before the TLB lookup.
TLB write: Ignored.
4
PL
PL Bit:
TLB lookup: If PL = 1, read hit occurred. If PL = 0, read miss occurred.
TLB write: If PL = 1, REP field is used to select the set. If PL = 0, the pseudo-LRU replacement algo-
rithm is used to select the set.
3:2
REP
Set Selection:
TLB lookup: If PL = 1, this field indicates the set in which the tag was found. If PL = 0, undefined data.
TLB write: If PL = 1, this field selects one of the four sets for replacement. If PL = 0, ignored.
1:0
TR6 Register
31:12
Linear
Address
Linear Address:
TLB lookup: The TLB is interrogated per this address. If one and only one match occurs in the TLB, the
rest of the fields in TR6 and TR7 are updated per the matching TLB entry.
TLB write: A TLB entry is allocated to this linear address.
11
V
Valid Bit:
TLB write: If V = 1, the TLB entry contains valid data. If V = 0, target entry is invalidated.
10:9
8:7
6:5
D, D#
U, U#
R, R#
Dirty Attribute Bit and its Complement (D, D#):
User/Supervisor Attribute Bit and its Complement (U, U#):
Read/Write Attribute Bit and its Complement (R, R#):
Effect on TLB Lookup
00 =
01 =
10 =
11 =
4:1
0
RSVD
C
Do not match
Match if D, U, or R bit is a 0
Match if D, U, or R bit is a 1
Match if D, U, or R bit is either a 1 or 0
Effect on TLB Write
Undefined
Clear the bit
Set the bit
Undefined
RSVD
Reserved:
Set to 0.
TLB Test Control Register (R/W)
Name
Description
TLB Test Data Register (R/W)
Reserved:
Set to 0.
Command Bit:
If C = 1: TLB lookup.
If C = 0: TLB write.
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