K1C6416B8D-FI70T
| Model | K1C6416B8D-FI70T |
| Description | Memory IC, 4MX16, CMOS, PBGA54 |
| PDF file | Total 47 pages (File size: 1M) |
| Chip Manufacturer | SAMSUNG |
K1C6416B8D
WAIT Configuration (BCR[8]) Default = 1 CLK Prior.
UtRAM2
The WAIT signal is output signal indicating the status of the data on the bus whether or not it is valid. WAIT configuration is to
decide the timing when WAIT asserts or desserts. WAIT asserts (or desserts) one clock prior to the data when A/DQ8 is set to 0.
(WAIT asserts (or desserts) at data clock when A/DQ8 is set to 1). WAIT polarity is to decide the WAIT signal level at which data is
valid or invalid. Data is valid if WAIT signal is high when A/DQ10 is set to 0. (Data is valid if WAIT signal is low when A/DQ10 is set
to 1). All the timing diagrams in this SPEC are illustrated based on following setup; A/DQ[10]:0 and A/DQ[8]:1.
Below timing shows WAIT signal’s movement when word boundary crossing happens in No-wrap mode
WAIT Polarity (BCR[10]) Default = Active HIGH
The WAIT polarity bit indicates whether an asserted WAIT output should be HIGH or LOW. This bit will determine whether the
WAIT signal requires a pull-up or pull-down resistor to maintain the de-asserted state.
WAIT Configuration During Burst Operation
No-Wrap. Word-line Crossing. LATENCY : 2. WP : Low Enable
0
CLOCK
1
2
3
4
5
6
7
8
9
10
11
12
13
ADV
Word-line Crossing period
(Only exists in No-wrap mode or Continuous mode)
A/DQ
Valid
Address
D253
D254
D255
D256
D257
D258
D259
D260
D261
D262
1CLK
1CLK
1CLK
WAIT
A/DQ[8]:1
de-assertion
assertion
de-assertion
WAIT
A/DQ[8]:0
de-assertion
assertion
de-assertion
Note: Non-default BCR setting: WAIT active LOW.
Operating Mode (BCR[15]) Default = Asynchronous Operation
The operating mode bit selects either synchronous burst operation or the default asynchronous mode of operation.
Latency Counter (BCR[13:11]) Default = 3 Clock Latency
The latency counter bits determine how many clocks occur between the beginning of a READ or WRITE operation and the first
data value transferred. For allowable latency codes.
Initial Access Latency (BRC[14]) Default = Variable
Variable initial access latency outputs data after the number of clocks set by the latency counter. However, WAIT must be moni-
tored to detect delays caused by collisions with refresh operations. Fixed initial access latency outputs the first data at a consistent
time that allows for worst-case refresh collisions. The latency counter must be configured to match the initial latency and the clock
frequency. It is not necessary to monitor WAIT with fixed initial latency. The burst begins after the number of clock cycles config-
ured by the latency counter.
-7-
Revision 3.0
Sep 2007
