K1C6416B8D-FI70T
| Model | K1C6416B8D-FI70T |
| Description | Memory IC, 4MX16, CMOS, PBGA54 |
| PDF file | Total 47 pages (File size: 1M) |
| Chip Manufacturer | SAMSUNG |
K1C6416B8D
CRE (CONTROL REGISTER ENABLE)
UtRAM2
The control registers store the values for the various modes to make UtRAM suitable for a various applications. The configuration
register values are written via A/DQ pins. In an asynchronous WRITE, the values are latched into the configuration register on the
rising edge of ADV, CS, or WE, whichever occurs first; LB and UB are “Don’t Care.” For reads, address inputs other than A[19:18]
are “Don’t Care,” and register bits 15:0 are output as data (ADV HIGH) on A/DQ[15:0]. Immediately after performing a configura-
tion register READ or WRITE operation, reading the memory array is highly recommended.
Bus Configuration Register
The BCR defines how the device interacts with the system memory bus. The BCR is accessed with CRE HIGH and A[19:18] =
10b, or through the register access software sequence with A/DQ = 0001h on the third cycle.
A19~A18
RS
A/DQ15
OM
A/DQ14
IL
A/DQ13~A/DQ11
LC
A/DQ10
WP
A/DQ8
WC
A/DQ5~A/DQ4
DS
A/DQ3
BW
A/DQ2~A/DQ0
BL
Register Select
A19
0
1
0
A18
0
0
1
RS
RCR
BCR
DIDR
0
1
Operating Mode
A/DQ15
OM
Synch.
Asynch (default)
0
1
Initial Latency
A/DQ14
IL
Variable (default)
Fixed
A/DQ13
0
0
0
0
1
1
1
1
Latency Count
A/DQ12
0
0
1
1
0
0
1
1
A/DQ11
0
1
0
1
0
1
0
1
LC
0
1
2
3 (default)
4
5
6
7
Wait Polarity
A/DQ10
0
1
WP
Active Low
Active High (default)
Wait Config.
A/DQ8
0
1
WC
at data
1 CLK prior
(default)
0
0
1
1
Driver Strength
A/DQ5 A/DQ4
0
1
0
1
DS
Full Drive
1/2 Drive
(default)
1/4 Drive
Reserved
Burst Wrap
A/DQ3
0
1
BW
Wrap
No Wrap
(default)
0
0
0
1
1
Burst Length
A/DQ2 A/DQ1 A/DQ0
0
1
1
0
1
1
0
1
0
1
BL
4 word
8 word
16 word
32 word
Continuous
(default)
1. A/DQ6, A/DQ7, A/DQ9, A16, A17, A20, A21 are reserved and should be ’1’
2. The registers are set automatically to default value.
3. Refresh command will be denied during continuous operation. CS low should not be longer than tBC(max. 2.5us)
Refresh Configuration Register
The refresh configuration register (RCR) defines how the device performs its self refresh. Altering the refresh parameters can
reduce current consumption during standby mode. The RCR is accessed with CRE HIGH and A[19:18] = 00b; or through the reg-
ister access software sequence with A/DQ = 0000h on the third cycle.
A19~A18
RS
A/DQ4
DPD
A/DQ2~A/DQ0
PAR
Register Select
A19
0
1
0
Deep Power Down
RS
RCR
BCR
DIDR
Partial Refresh
A/DQ2
0
0
0
0
1
1
1
1
A18
0
0
1
A/DQ4
0
1
DPD
Enable
Disable (default)
A/DQ1
0
0
1
1
0
0
1
1
A/DQ0
0
1
0
1
0
1
0
1
PAR
Full Array (default)
Bottom 1/2 Array
Bottom 1/4 Array
Bottom 1/8 Array
None of Array
Bottom 1/2 Array
Bottom 1/4 Array
Bottom 1/8 Array
1. A/DQ3, A/DQ5~A/DQ15, A16, A17, A20, A21 are reserved and should be ’1’
2. The registers are set automatically to default value.
-5-
Revision 3.0
Sep 2007
