K1C6416B8D-FI70T
| Model | K1C6416B8D-FI70T |
| Description | Memory IC, 4MX16, CMOS, PBGA54 |
| PDF file | Total 47 pages (File size: 1M) |
| Chip Manufacturer | SAMSUNG |
K1C6416B8D
PIN DESCRIPTIONS & FUNCTION BLOCK DIAGRAM
1
2
3
4
5
6
Clk gen.
UtRAM2
Pre-charge circuit
V
CC
V
CCQ
V
SS
V
SSQ
A
LB
OE
RFU
RFU
RFU
CRE
B
A/DQ8
UB
RFU
RFU
CS
A/DQ0
Row
Addresses
Row
select
Memory
Array
C
A/DQ9
A/DQ10
RFU
RFU
A/DQ1
A/DQ2
A16~A21
D
VssQ
A/DQ11
A17
RFU
A/DQ3
Vcc
A/DQ
0
~A/DQ
7
Data
cont
Data
cont
Data
cont
I/O Circuit
E
F
Column Select
VccQ
A/DQ12
A21
A16
A/DQ4
Vss
A/DQ
8
~A/DQ
15
A/DQ14 A/DQ13
RFU
RFU
A/DQ5
A/DQ6
Column Address
G
A/DQ15
A19
RFU
RFU
WE
A/DQ7
H
J
A18
RFU
RFU
RFU
RFU
A20
CLK
CS
ADV
OE
WE
UB
LB
CRE
WAIT
CLK
ADV
RFU
RFU
RFU
Control Logic
54-FBGA - 6.00 x 8.00
Top View (Ball Down)
WAIT
BALL DESCRIPTIONS
Symbol
A/DQ[15:0]
A[21:16]
CLK
(note1)
ADV
(note1)
CRE
CS
OE
WE
LB
UB
WAIT
(note1)
RFU
V
CC
V
CCQ
V
SS
V
SSQ
Type
Input /
Output
Input
Input
Description
Address / Data I/Os: These pins are a multiplexed address/data bus. As inputs for addresses, these pins behave as
A[15:0]; These lines are also used to define the value to be loaded into the BCR or the RCR.
Address Inputs for addresses during READ and WRITE operations.
Clock: Synchronizes the memory to the system operating frequency during synchronous operations. When configured
for synchronous operation, the address is latched on the first rising CLK edge when ADV is active. CLK is static LOW
during asynchronous access READ and WRITE operations.
Address valid: Indicates that a valid address is present on the address inputs. Addresses can be latched on the rising
edge of ADV during asynchronous READ and WRITE operations. ADV can be held LOW during asynchronous READ
and WRITE operations.
Control register enable: When CRE is HIGH, WRITE operations load the RCR or BCR, and READ operations access
the RCR, BCR, or DIDR.
Chip Select: Activates the device when LOW. When CS is HIGH, the device is disabled and goes into standby or deep
power-down mode.
Output enable: Enables the output buffers when LOW. When OE is HIGH,
the output buffers are disabled.
Write enable: Determines if a given cycle is a WRITE cycle. If WE is LOW, the cycle is a WRITE to either a configura-
tion register or to the memory array.
Lower byte enable. DQ[7:0]
Upper byte enable. DQ[15:8]
Wait: Provides data-valid feedback during burst READ and WRITE operations. The signal is gated by CS. WAIT is
used to arbitrate collisions between refresh and READ/WRITE operations. WAIT is also asserted during row boundary
crossing within the burst length. WAIT is asserted and should be ignored during asynchronous operations. WAIT is
High-Z when CS is HIGH.
Reserved for Future Use
Device power supply: (1.70V–1.95V) Power supply for device core operation.
I/O power supply: (1.70V–1.95V) Power supply for input/output buffers.
V
SS
must be connected to ground.
V
SSQ
must be connected to ground.
Input
Input
Input
Input
Input
Input
Input
Output
-
Supply
Supply
Supply
Supply
1. When using asynchronous mode exclusively, the CLK and ADV inputs can be tied to V
SS
. WAIT will be asserted but should be ignored during
asynchronous mode operations.
-2-
Revision 3.0
Sep 2007
