K1C6416B8D-FI70T
| Model | K1C6416B8D-FI70T |
| Description | Memory IC, 4MX16, CMOS, PBGA54 |
| PDF file | Total 47 pages (File size: 1M) |
| Chip Manufacturer | SAMSUNG |
K1C6416B8D
Variable Latency Configuration Codes
BCR[13:11]
010
011
Others
Latency Configuration
2(3 clocks)
3(4 clocks)-default
Reserved
Latency
Normal
2
3
-
Refresh Collision
4
6
-
UtRAM2
Max Input CLK Frequency (MHz)
104
66(15ns)
104(9.62ns)
-
80
52(19,2ns)
80(12.5ns)
-
66
40(25ns)
66(15ns)
-
Fixed Latency Configuration Codes
BCR[13:11]
010
011
100
101
110
Others
Latency Configuration
2 (3 clocks)
3 (4 clocks)
4 (5 clocks)
5 (6 clocks)
6 (7 clocks)
Reserved
Latency Count (N)
2
3
4
5
6
-
Max Input CLK Frequency (MHz)
104
33 (30ns)
52 (19.2ns)
66 (15ns)
80 (12.5ns)
104 (9.62ns)
-
80
20 (50ns)
40 (25ns)
52 (19.2ns)
66 (15ns)
80 (12.5ns)
-
66
20 (50ns)
33 (30ns)
40 (25ns)
52 (19.2ns)
66 (15ns)
-
1. Latency is the number of clock cycles from the initiation of a burst operation until data appears. Data is transferred on the next clock cycle.
Latency Counter (Variable Initial Latency, No Refresh Collision)
CLK
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
VALID
ADDRESS
Code 2
VALID
ADDRESS
Code 3 (Default)
ADV
A[21:16]
A/DQ[15:0]
V
OH
V
OL
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
A/DQ[15:0]
VALID
ADDRESS
Code 4
VALID
ADDRESS
V
OH
V
OL
Valid
Output
Valid
Output
Valid
Output
Valid
Output
A/DQ[15:0]
V
OH
V
OL
Valid
Output
Valid
Output
Valid
Output
Don’t Care
Latency Counter (Fixed Latency)
N-1 Cycles
CLK
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
t
AA
A/DQ[15:0]
(READ)
A/DQ[15:0]
(WRITE)
V
IH
V
IL
V
IH
V
IL
VALID
ADDRESS
VALID
ADDRESS
Undefined
N Cycle
t
AADV
ADV
A[21:16]
t
CO
t
ACLK
V
OH
V
OL
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
CS
t
SP
t
HD
Valid
Input
Valid
Input
Valid
Input
Valid
Input
Valid
Input
VALID
ADDRESS
Burst Identified
(ADV = LOW)
Don’t Care
Undefined
-8-
Revision 3.0
Sep 2007
