K1C6416B8D-FI70T
| Model | K1C6416B8D-FI70T |
| Description | Memory IC, 4MX16, CMOS, PBGA54 |
| PDF file | Total 47 pages (File size: 1M) |
| Chip Manufacturer | SAMSUNG |
K1C6416B8D
Mixed-Mode Operation
UtRAM2
The device supports a combination of synchronous READ and asynchronous WRITE operations when the BCR is configured for
synchronous operation. The asynchronous WRITE operations require that the clock (CLK) remain LOW during the entire
sequence. The ADV signal can be used to latch the target address, CS can remain LOW when transitioning between mixed-mode
operations with fixed latency enabled; however, the CS LOW time must not exceed tCSM. Mixed-mode operation facilitates a
seamless interface to legacy burst mode Flash memory controllers.
Burst Suspend
To access other devices on the same bus without the timing penalty of the initial latency for a new burst, burst mode can be sus-
pended. Bursts are suspended by stopping CLK. CLK can be stopped HIGH or LOW. If another device will use the data bus while
the burst is suspended, OE should be taken HIGH to disable the outputs. otherwise, OE can remain LOW. Note that the WAIT out-
put will continue to be active, and as a result no other devices should directly share the WAIT connection to the controller. To con-
tinue the burst sequence, OE is taken LOW, then CLK is restarted after valid data is available on the bus. The CS LOW time is
limited by refresh considerations. CS must not stay LOW longer than tCSM. If a burst suspension will cause CS to remain LOW for
longer than tCSM, CS should be taken HIGH and the burst restarted with a new CS LOW/ADV LOW cycle.
Boundary Crossing
Continuous bursts or No wrap burst have the ability to start at a specified address and burst to the end of the address. It goes back
to the first address and continues the burst operation. WAIT will be asserted at the boundary of the row and be desserted after
crossing boundary of the row.
WAIT Operation
The WAIT output is typically connected to a shared systemlevel WAIT signal. The shared WAIT signal is used by the processor to
coordinate transactions with multiple memories on the synchronous bus. Once a READ or WRITE operation has been initiated,
WAIT goes active to indicate that additional time is required before data can be transferred. For READ operations, WAIT will
remain active until valid data is output from the device. For WRITE operations, WAIT will indicate to the memory controller when
data will be accepted into this device. When WAIT transitions to an inactive state, the data burst will progress on successive clock
edges. CS must remain asserted during WAIT cycles (WAIT asserted and WAIT configuration BCR[8] = 1). Bringing CS HIGH dur-
ing WAIT cycles may cause data corruption. (Note that for BCR[8] = 0, the actual WAIT cycles end one cycle after WAIT de-
asserts. When using variable initial access latency (BCR[14] = 0), the WAIT output performs an arbitration role for READ opera-
tions launched while an on-chip refresh is in progress. If a collision occurs, WAIT is asserted for additional clock cycles until the
refresh has completed. When the refresh operation has completed, the READ operation will continue normally. WAIT will be
asserted but should be ignored during asynchronous READ and WRITE operations. By using fixed initial latency (BCR[14] = 1),
this device can be used in burst mode without monitoring the WAIT signal. However, WAIT can still be used to determine when
valid data is available at the start of the burst.
Wired or WAIT Configuration
UtRAM2
WAIT
READY
WAIT
Processor
Other
Device
RDY
Other
Device
External
Pull-Up
Pull-Down
Resistor
LB / UB Operation
The LB enable and UB enable signals support byte-wide data WRITEs. During WRITE operations, any disabled bytes will not be
transferred to the RAM array and the internal value will remain unchanged. During an asynchronous WRITE cycle, the data to be
written is latched on the rising edge of CS, WE, LB, or UB, whichever occurs first. LB and UB must be LOW during READ cycles.
When both the LB and UB are disabled (HIGH) during an operation, the device will disable the data bus from receiving or transmit-
ting data. Although the device will seem to be deselected, it remains in an active mode as long as CS remains LOW.
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Revision 3.0
Sep 2007
