K1C6416B8D-FI70T
| Model | K1C6416B8D-FI70T |
| Description | Memory IC, 4MX16, CMOS, PBGA54 |
| PDF file | Total 47 pages (File size: 1M) |
| Chip Manufacturer | SAMSUNG |
K1C6416B8D
Asynchronous READ Followed by WRITE at the Same Address
(CRE=V
IL
)
A[21:16]
V
IH
V
IL
UtRAM2
Valid Address
t
AVS
t
VP
t
BA
t
BW
t
AADV
ADV
V
IH
V
IL
LB/UB
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
t
CSW
High-Z
t
CPH
t
CVP
t
CO
t
ADVOE
t
OE
t
OHZ
CS
OE
t
OLZ
t
WHZ
WE
t
WP
NOTE2
WAIT
V
OH
V
OL
t
AA
t
AVS
t
AVH
V
OH
V
OL
t
DS
t
DH
V
IH
V
IL
A/DQ[15:0]
V
IH
IN/OUT
V
IL
Valid Address
Valid Output
Valid Input
Don’t Care
Undefined
1. The end of the WRITE cycle is controlled by CS, LB/UB, or WE, whichever de-asserts first.
2. WE must not remain LOW longer than 2.5µs (tCSM) while the device is selected (CS LOW).
3. Don’t care must be in V
IL
or V
IH
.
- 42 -
Revision 3.0
Sep 2007
