K1C6416B8D-FI70T
| Model | K1C6416B8D-FI70T |
| Description | Memory IC, 4MX16, CMOS, PBGA54 |
| PDF file | Total 47 pages (File size: 1M) |
| Chip Manufacturer | SAMSUNG |
K1C6416B8D
UtRAM2
The size of a burst can be specified in the BCR either as a fixed length or continuous. Fixed-length bursts consist of four, eight,
sixteen, or thirty-two words. The initial latency for READ operations can be configured as fixed or variable (WRITE operations
always use fixed latency). Variable latency allows minimum latency at high clock frequencies, but the controller must monitor
WAIT to detect any conflict with refresh cycles. Fixed latency outputs the first data word after the worst-case access delay, includ-
ing allowance for refresh collisions. The initial latency time and clock speed determine the latency count setting. Fixed latency is
used when the controller cannot monitor WAIT. Fixed latency also provides improved performance at lower clock frequencies.
Refresh Collision During Variable-Latency READ Operation
CLK
A[21:16]
ADV
CS
OE
WE
LB/UB
WAIT
A/DQ[15:0]
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
OH
V
OL
V
IH
V
IL
Address
Valid
Address
Valid
High-Z
V
OH
V
OL
D[0]
D[1]
D[2]
D[3]
Undefined
Additional WAIT states inserted to allow refresh completion.
Don’t Care
1. Non-default BCR settings for refresh collision during variable-latency READ operation:
2. Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay.
Functional Description (Synch. mode)
Burst Mode
BCR[15] = 0
Async read
Async write
Standby
No operation
Initial burst read
Initial burst write
Burst continue
Burst suspend
Configuration register
write
Configuration register
read
DPD
Power
Active
Active
Standby
Idle
Active
Active
Active
Active
Active
Active
Deep power-
down
L
X
CLK
L
L
L
L
H
X
L
L
H
X
L
L
X
ADV
CS
L
L
H
L
L
L
L
L
L
L
H
OE
L
H
X
X
X
H
X
H
H
L
X
WE
H
L
X
X
H
L
X
X
L
H
X
CRE
L
L
L
L
L
L
X
X
H
H
X
UB /
LB
L
L
X
X
L
X
L
X
X
L
X
WAIT
Low-Z
High-Z
High-Z
Low-Z
Low-Z
Low-Z
Low-Z
Low-Z
Low-Z
Low-Z
High-Z
A/DQ[15:0]
Data out
Data in
High-Z
X
Address
Address
Data in or
Data out
High-Z
High-Z
Config.
reg.out
High-Z
3
3
Notes
3
3
4
4
1. CLK must be LOW during async read and async write modes.
2. When LB and UB are in select mode (LOW), A/DQ[15:0] are affected. When only LB is in select mode, A/DQ[7:0] are affected. When only UB is in
the select mode, A/DQ[15:8] are affected.
3. The device will consume active power in this mode whenever addresses are changed.
4. When the device is in standby mode, address inputs and data inputs/outputs are internally isolated from any external influence.
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Revision 3.0
Sep 2007
