K1C6416B2D-BI70
| Model | K1C6416B2D-BI70 |
| Description | Memory IC, 4MX16, CMOS, PBGA54 |
| PDF file | Total 50 pages (File size: 1M) |
| Chip Manufacturer | SAMSUNG |
K1C6416B2D
Partial Array Refresh (RCR[2:0]) Default = Full Array Refresh
UtRAM2
The PAR bits restrict refresh operation to a portion of the total memory array. This feature allows the device to reduce standby cur-
rent by refreshing only that part of the memory array required by the host system. The refresh options are full array, one-half array,
one-quarter array, one-eighth array, or none of the array. The mapping of these partitions can start at either the beginning or the
end of the address map.
Address Patterns for PAR (RCR[4] = 1)
RCR[2]
0
0
0
0
1
1
1
1
RCR[1]
0
0
1
1
0
0
1
1
RCR[0]
0
1
0
1
0
1
0
1
Active Section
Full Die
One-half die
One-quarter of die
One-eighth of die
None of die
One-half of die
One-quarter of die
One-eighth of die
Address Space
000000h-3FFFFFh
000000h-1FFFFFh
000000h-0FFFFFh
000000h-07FFFFh
0
200000h-3FFFFFh
300000h-3FFFFFh
380000h-3FFFFFh
Size
4 Meg x 16
2 Meg x 16
1 Meg x 16
512K x 16
0 Meg x 16
2 Meg x 16
1 Meg x 16
512K x 16
Density
64Mb
32Mb
16Mb
8Mb
0Mb
32Mb
16Mb
8Mb
Deep Power-Down (RCR[4]) Default = DPD Disabled
The deep power-down bit enables and disables all refresh-related activity. This mode is used if the system does not require the
storage provided by this memory. Any stored data will become corrupted when DPD is enabled. When refresh activity has been
re-enabled, the device will require 150µs to perform an initialization procedure before normal operations can resume. Deep
power-down is enabled by setting RCR[4] = 0 and taking CS HIGH. DPD can be enabled using CRE or the software sequence to
access the RCR. Taking CS LOW for at least 10µs disables DPD and sets RCR[4] = 1. it is not necessary to write to the RCR to
disable DPD. BCR and RCR values (other than BCR[4]) are preserved during DPD.
DPD Entry and Exit Timing Parameters & Initialization and DPD Timing Parameters
tDPD
CS
Write
RCR[4] = 0
DPD Enabled
tDPDX
tPU
Symbol
tDPD
tDPDX
DPD EXIT
Device Initialization
tPU
Min
10
10
150
Max
Unit
µs
µs
µs
Device Identification Register
The DIDR provides information on the device manufacturer, generation and the specific device configuration. This register is read-
only. The DIDR is accessed with CRE HIGH and A[19:18] = 01b, or through the register access software sequence with A= 0002h
on the third cycle.
Device Identification Register Mapping
Bit Field
Field name
DIDR[15]
Row Length
Length
Options
256 words
Bit
Setting
1b
DIDR[14:11]
Device version
Version
5th
Bit
Setting
100b
DIDR[10:8])
Device density
Density
64Mb
Bit
Setting
010b
DIDR[7:5]
UtRAM generation
Generation
UtRAM2
Bit
Setting
010b
DIDR[4:0]
Vendor ID
Bit
Setting
01100
-9-
Revision 3.0
Sep 2007
