K1C6416B2D-BI70
| Model | K1C6416B2D-BI70 |
| Description | Memory IC, 4MX16, CMOS, PBGA54 |
| PDF file | Total 50 pages (File size: 1M) |
| Chip Manufacturer | SAMSUNG |
K1C6416B2D
Asynchronous WRITE Followed by Asynchronous READ
(CRE=V
IL
)
V
IH
V
IL
V
IH
V
IL
V
IH
LB/UB
V
IL
t
CW
CS
V
IH
V
IL
V
IH
V
IL
t
AS
WE
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
t
CSW
t
WHZ
High-Z
UtRAM2
A[21:0]
Valid Address
t
AVS
t
VP
Valid Address
t
AW
t
VS
t
WR
Valid Address
t
AA
ADV
t
CVS
t
BW
t
CPH
t
BLZ
t
BHZ
t
HZ
t
AS
Note 1
t
LZ
t
OHZ
OE
t
WP
t
WC
t
WPH
t
OLZ
WAIT
DQ[15:0]
IN/OUT
t
OE
Data
t
DH
Data
t
DW
V
OH
V
OL
High-Z
Valid Output
Don’t Care
Undefined
Notes:
1. When configured for synchronous mode (BCR[15] = 0), CS must remain HIGH for at least 5ns (tCPH) to schedule the appropriate refresh interval.
Otherwise, tCPH is only required after CS-controlled WRITEs.
2. Don’t care must be in V
IL
or V
IH
.
- 45 -
Revision 3.0
Sep 2007
