K1C6416B2D-BI70
| Model | K1C6416B2D-BI70 |
| Description | Memory IC, 4MX16, CMOS, PBGA54 |
| PDF file | Total 50 pages (File size: 1M) |
| Chip Manufacturer | SAMSUNG |
K1C6416B2D
Burst Mode Operation
UtRAM2
Synchronous Burst Read Operation
Burst Read command is implemented when ADV is detected low at clock rising edge. WE should be de-asserted. Burst operation
re-starts whenever ADV is detected low at clock rising edge even in the middle of operation.
Synchronous Burst Write Operation
Burst Write command is implemented when ADV & WE are detected low at clock rising edge. Burst Write operation re-starts
whenever ADV is detected low at clock rising edge even in the middle of Burst Write operation.
Burst Mode READ (4-word burst)
0
1
2
3
4
5
6
7
8
9
10
11
12
CLK
CS
A[21:0]
ADV
OE
WE
LB/UB
WAIT
DQ[15:0]
Latency Code 3 (4 clocks)
READ Burst Identified
(WE = HIGH)
READ Burst Identified
(WE = HIGH)
Don’t Care
Undefined
1. Non-default BCR settings for burst mode READ (4-word burst): Fixed or variable latency;
2. Latency code 3 (4 clocks); WAIT active LOW; WAIT asserted during delay.
3. Diagram in the figure above is representative of variable latency with no refresh collision or fixed-latency access.
Burst Mode WRITE (4-word burst)
0
1
2
3
4
5
6
7
8
9
10
11
12
CLK
CS
A[21:0]
ADV
Latency Code 3 (4 clocks)
WE
LB/UB
WAIT
DQ[15:0]
WRITE Burst Identified
(WE = LOW)
READ Burst Identified
(WE = HIGH)
Don’t Care
1. Non-default BCR settings for burst mode WRITE (4-word burst): Fixed or variable latency;
2. Latency code 3 (4 clocks); WAIT active LOW; WAIT asserted during delay.
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Revision 3.0
Sep 2007
