K1C6416B2D-BI70
| Model | K1C6416B2D-BI70 |
| Description | Memory IC, 4MX16, CMOS, PBGA54 |
| PDF file | Total 50 pages (File size: 1M) |
| Chip Manufacturer | SAMSUNG |
K1C6416B2D
ABSOLUTE MAXIMUM RATINGS
Item
Voltage on any pin relative to Vss
Power supply voltage relative to Vss
Power Dissipation
Storage temperature
Operating Temperature
UtRAM2
Symbol
V
IN
, V
OUT
V
CC
, V
CCQ
P
D
T
STG
T
A
Ratings
-0.2 to V
CCQ
+0.3V
-0.2 to 2.5V
1.0
-65 to 150
-40 to 85
Unit
V
V
W
°C
°C
1) Stresses greater than "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be restricted to be
used under recommended operating condition. Exposure to absolute maximum rating conditions longer than 1 second may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS
Item
Power supply voltage(Core)
Power supply voltage(I/O)
Ground
Input high voltage
Input low voltage
Symbol
V
CC
V
CCQ
V
SS
, V
SSQ
V
IH
V
IL
Min
1.7
1.7
0
V
CCQ
-0.4
-0.2
3)
Typ
1.8
1.8
0
-
-
Max
1.95
1.95
0
V
CCQ
+0.2
2)
0.4
Unit
V
V
V
V
V
1. T
A
=-40 to 85°C, otherwise specified.
2. Overshoot: V
CCQ
+1.0V in case of pulse width
≤20ns.
Overshoot is sampled, not 100% tested.
3. Undershoot: -1.0V in case of pulse width
≤20ns.
Undershoot is sampled, not 100% tested.
CAPACITANCE
Item
Input capacitance
Input/Output capacitance
1. Freq.=1MHz, T
A
=25°C
2. Capacitance is sampled, not 100% tested.
Symbol
C
IN
C
IO
Test Condition
V
IN
=0V
V
IO
=0V
Min
-
-
Max
8
8
Unit
pF
pF
DC AND OPERATING CHARACTERISTICS
Item
Input Leakage Current
Output Leakage Current
Average Operating
Current (Async)
Average Operating
Current (Burst)
Output Low Voltage
Output High Voltage
Standby Current(CMOS)
Symbol
I
LI
I
LO
I
CC26)
I
CC2P
I
CC3
V
OL
V
OH
I
SB11)
V
IN
=Vss to V
CCQ
Test Conditions
CS=V
IH,
CRE=V
IL
, OE=V
IH
or WE=V
IL
, V
IO
=V
SS
to V
CCQ
Cycle time=min tRC/min tWC, I
IO
=0mA
4)
, 100% duty, CS=V
IL
,
CRE=V
IL
,
V
IN
=V
IL
or V
IH
Cycle time=min tRC+3 min tPC, I
IO
=0mA
4)
, 100% duty, CS=V
IL
,
CRE=V
IL
,
V
IN
=V
IL
or V
IH
Burst Length 4, Latency 5, 80MHz, I
IO
=0mA
4)
, Address transition 1
time, CS=V
IL
, CRE=V
IL
,
V
IN
=V
IL
or V
IH
I
OL
=0.2mA
I
OH
=-0.2mA
CS=V
CCQ
, CRE=0V, Other inputs=0V or V
CCQ
(Toggle is not allowed)
5)
< 40°C
< 85°C
1/2 Block
< 40°C
1/4 Block
1/8 Block
1/2 Block
< 85°C
1/4 Block
1/8 Block
CS=V
CCQ
, CRE=0V, Other inputs=0V or V
CCQ
(Toggle is not allowed)
5)
Min
-1
-1
-
-
-
-
1.4
-
-
-
-
-
-
-
-
-
Typ
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Max
1
1
40
40
40
0.2
-
120
180
115
110
105
165
155
145
30
Unit
µA
µA
mA
mA
mA
V
V
µA
µA
µA
Partial Refresh Current
I
SBP2)
µA
µA
Deep Power Down Current
I
SBD
CRE=0V, CS=V
CCQ
, Other inputs=0V or V
CCQ
(Toggle is not allowed)
5)
1. I
SB1
is measured after 60ms after CS high. CLK should be fixed at high or at Low.
2. Full Array Partial Refresh Current(I
SBP
) is same as Standby Current(I
SB1
).
3. Internal TCSR (Temperature Compensated Self Refresh) is used to optimize refresh cycle below 40°C.
4. I
IO
=0mA; This parameter is specified with the outputs disabled to avoid external loading effects.
5. V
IN
=0V; all inputs should not be toggle.
6. Clock should not be inserted between ADV low and WE low during Write operation.
-4-
Revision 3.0
Sep 2007
