K1C6416B2D-BI70
Model | K1C6416B2D-BI70 |
Description | Memory IC, 4MX16, CMOS, PBGA54 |
PDF file | Total 50 pages (File size: 1M) |
Chip Manufacturer | SAMSUNG |
K1C6416B2D
Burst WRITE Interrupted by Burst WRITE or READ—Variable Latency Mode
(CRE=V
IL
)
t
CLK
V
IH
CLK
V
IL
t
SP
A[21:0]
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
OH
High-Z
V
OL
t
CSW
t
SP
t
HD
t
KHTL
t
CSP
t
SP
t
HD
t
SP
t
HD
t
AHCR
t
AHCR
t
CSM (Note 3)
t
HD
UtRAM2
WRITE Burst interrupted with new WRITE or READ. See Note 2.
t
HD
t
SP
t
HD
Valid
Address
Valid
Address
t
SP
t
HD
ADV
t
SP
t
HD
CS
WE
WAIT
High-Z
OE
V
IH
2nd Cycle WRITE
V
IL
LB/UB
V
IH
2nd Cycle WRITE
V
IL
High-Z
t
SP
t
HD
D0
t
SP
t
HD
D0
D1
D2
D3
DQ[15:0]IN
V
IH
2nd Cycle WRITE
V
IL
t
BOE
OE
V
IH
2nd Cycle READ
V
IL
LB/UB
V
IH
2nd Cycle READ
V
IL
V
OH
V
OL
V
OH
High-Z
t
OHZ
t
SP
t
KOH
Valid
Output
Valid
Output
Valid
Output
Valid
Output
DQp15:0]OUT
2nd Cycle READ
V
OL
t
ACLK
Don’t Care
Undefined
Notes:
1. Non-default BCR settings for burst WRITE interrupted by burst WRITE or READ in variable latency mode: Variable latency; latency code two
(three clocks); WAIT active LOW; WAIT asserted during delay. All bursts shown for variable latency; no refresh collision.
2. Burst interrupt shown on first allowable clock (i.e., after first data word written).
3. CS can stay LOW between burst operations, but CS must not remain LOW longer than tCSM.
4. Don’t care must be in V
IL
or V
IH
.
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Revision 3.0
Sep 2007