K1C6416B2D-BI70
| Model | K1C6416B2D-BI70 |
| Description | Memory IC, 4MX16, CMOS, PBGA54 |
| PDF file | Total 50 pages (File size: 1M) |
| Chip Manufacturer | SAMSUNG |
K1C6416B2D
Register READ, Asynchronous Mode Followed by READ ARRAY Operation
A[21:0]
(except A[19:18])
t
AVS
A[19:18]
1
Select Register
t
AA
CRE
t
AVS
t
AA
ADV
t
VP
CS
OE
t
AAVD
Initiate Register Access
t
CO
t
OE
WE
t
OLZ
t
LZ
LB/UB
t
LZ
DQ[15:0]
t
BA
t
CPH
t
HZ
t
AVH
UtRAM2
ADDRESS
ADDRESS
t
OHZ
t
BHZ
CR Valid
Data Valid
Don’t Care
Undefined
1. A[19:18] = 00b to read RCR, 10b to read BCR, and 01b to read DIDR.
Register READ, Synchronous Mode Followed by READ ARRAY Operation
CLK
A[21:0]
(except A[19:18])
A[19:18]
2
t
SP
CRE
t
SP
ADV
t
HD
CS
OE
t
BOE
t
SP
LB/UB
t
CW
WAIT
DQ[15:0]
High-Z
t
OLZ
t
ACLK
t
KOH
High-Z
Data
Valid
Latch Control Register Value
ADDRESS
t
SP
Latch Control Register Address
ADDRESS
t
HD
t
HD
t
ABA
t
CSP
t
CBPH
3
t
HZ
t
OHZ
t
HD
CR Valid
Don’t Care
Undefined
1. Non-default BCR settings for synchronous mode register READ followed by READ ARRAY operation: Latency code two (three clocks);
WAIT active LOW; WAIT asserted during delay.
2. A[19:18] = 00b to read RCR, 10b to read BCR, and 01b to read DIDR.
3. CS must remain LOW to complete a burst-of-one WRITE. WAIT must be monitored—additional WAIT cycles caused by refresh collisions require
a corresponding number of additional CS LOW cycles.
- 11 -
Revision 3.0
Sep 2007
