K1C6416B2D-BI70
| Model | K1C6416B2D-BI70 |
| Description | Memory IC, 4MX16, CMOS, PBGA54 |
| PDF file | Total 50 pages (File size: 1M) |
| Chip Manufacturer | SAMSUNG |
K1C6416B2D
WE-Controlled Asynchronous WRITE
(CRE=V
IL
)
t
WC
A[21:0]
V
IH
V
IL
UtRAM2
Valid Address
t
AW
t
WR
ADV
V
IH
V
IL
t
CW
CS
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
t
AS
t
WPH
t
BW
UB/LB
OE
t
WP
WE
V
IH
V
IL
High-Z
t
DW
t
WHZ
t
DH
DQ[15:0]
V
IH
IN
V
IL
DQ[15:0]
V
OH
OUT
V
OL
Valid Input
t
OW
t
LZ
t
CSW
WAIT
V
IH
V
IL
High-Z
t
HZ
High-Z
Don’t Care
1. Don’t care must be in V
IL
or V
IH
.
2. A wri
t
e occurs during the overlap(t
WP
) of low CS and low WE. A write begins when CS goes low and WE goes low with asserting UB or LB for sin-
gle byte operation or simultaneously asserting UB and LB for double byte operation. A write ends at the earliest transition when CS goes high or
WE goes high or UB/LB goes high. The t
WP
is measured from the beginning of write to the end of write.
3. t
CW
is measured from the CS going low to the end of write.
4. t
AS
is measured from the address valid to the beginning of write.
5. t
WR
is measured from the end of write to the address change. t
WR
is applied in case a write ends with CS or WE going high.
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Revision 3.0
Sep 2007
