K1C6416B2D-BI70
| Model | K1C6416B2D-BI70 |
| Description | Memory IC, 4MX16, CMOS, PBGA54 |
| PDF file | Total 50 pages (File size: 1M) |
| Chip Manufacturer | SAMSUNG |
K1C6416B2D
BUS OPERATING MODES
UtRAM2
The bus interface supports asynchronous and burst mode read and write transfers. The specific interface supported is defined by
the value loaded into the BCR.
Asynchronous Mode (default mode)
Asynchronous (Page) read operation
Asynchronous read operation starts when CS, OE and UB or LB are asserted. ADV can be taken HIGH to capture the address.
First data will be driven out of the DQ bus after random access time(tAA) and second, third and fourth data can be driven out after
page access time(tPA) when using the page addresses (A0, A1). WE should be de-asserted during read operation. The CLK input
must be held static LOW during read operation. WAIT will be driven while the device is enabled and its state should be ignored.
Asynchronous write operation
Asynchronous write operation starts when CS, WE and UB or LB are asserted. The data to be written is latched on the rising edge
of CS, WE, or LB/UB (whichever occurs first). OE is don’t care during write operation and WE will override OE. WE LOW time
must be limited to tCSM. The CLK input must be held static LOW during write operation. WAIT signal is Hi-Z.
READ Operation
(ADV = LOW, WE = HIGH).
< tCSM
WRITE Operation(ADV
= LOW, OE = HIGH)
CS
CS
Address
Add0
Add1 Add2 Add3
Address
Address Valid
< tCSM
OE
tAA
tAPA
tAPA
tAPA
WE
LB/UB
LB/UB
tWC = WRITE Cycle Time
Data
D0
D1
D2
D3
Don’t Care
DATA
High-Z
Data Valid
Don’t Care
Undefined
Functional Description (Asynch. mode)
Asynchfonous Mode
BCR[15] = 1
Read
Write
Standby
No operation
Configuration register
write
Configuration register
read
DPD
Power
Active
Active
Standby
Idle
Active
Active
Deep Power-
down
CLK
L
L
L
L
L
L
L
ADV
L
L
X
X
L
L
X
CS
L
L
H
L
L
L
H
OE
L
X
X
X
X
L
X
WE
H
L
X
X
L
H
X
CRE
L
L
L
L
H
H
X
UB /
LB
L
L
X
X
X
L
X
WAIT
Low-Z
Low-Z
High-Z
Low-Z
Low-Z
Low-Z
High-Z
DQ[15:0]
Data out
Data in
High-Z
X
High-Z
Config.
Reg.out
High-Z
7
Notes
4
4
5,6
4,6
1. CLK must be LOW during async read and async write modes; and to achieve standby power during standby and DPD modes. CLK must be static
(HIGH or LOW) during burst suspend.
2. The WAIT polarity is configured through the bus configuration register (BCR[10]).
3. When LB and UB are in select mode (LOW), DQ[15:0] are affected. When only LB is in select mode, DQ[7:0] are affected. When only UB is in the
select mode, DQ[15:8] are affected.
4. The device will consume active power in this mode whenever addresses are changed.
5. When the device is in standby mode, address inputs and data inputs/outputs are internally isolated from any external influence.
6. VIN = VCCQ or 0V; all device balls must be static (unswitched) in order to achieve standby current.
7. DPD is initiated when CS transitions from LOW to HIGH after writing RCR[4] to 0. DPD is maintained until CS transitions from HIGH to LOW.
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Revision 3.0
Sep 2007
