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K1C6416B2D-BI70

K1C6416B2D

LOW-POWER OPERATION

Temperature Compensated Self Refresh

UtRAM2

Temperature compensated self refresh (TCSR) allows for adequate refresh at different temperatures. This UtRAM2 device

includes an on-chip temperature sensor that automatically adjusts the refresh rate according to the operating temperature. The

device continually adjusts the refresh rate to match that temperature.

Partial Array Refresh

Partial array refresh (PAR) restricts refresh operation to a portion of the total memory array. This feature enables the device to

reduce standby current by refreshing only that part of the memory array required by the host system. The refresh options are full

array, one-half array, one-quarter array, one-eighth array, or none of the array. The mapping of these partitions can start at either

the beginning or the end of the address map. READ and WRITE operations to address ranges receiving refresh will not be

affected. Data stored in addresses not receiving refresh will become corrupted. When re-enabling additional portions of the array,

the new portions are available immediately upon writing to the RCR.

Deep Power-Down Operation

Deep power-down (DPD) operation disables all refresh-related activity. This mode is used if the system does not require the stor-

age provided by the UtRAM2 device. Any stored data will become corrupted when DPD is enabled. When refresh activity has

been re-enabled, the UtRAM2 device will require 150µs to perform an initialization procedure before normal operations can

resume. During this 150µs period, the current consumption will be higher than the specified standby levels, but considerably lower

than the active current specification. DPD can be enabled by writing to the RCR using CRE or the software access sequence;

DPD starts when CS goes HIGH. DPD is disabled the next time CS goes LOW and stays LOW for at least 10µs.

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Revision 3.0

Sep 2007

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