K1C6416B2D-BI70
| Model | K1C6416B2D-BI70 |
| Description | Memory IC, 4MX16, CMOS, PBGA54 |
| PDF file | Total 50 pages (File size: 1M) |
| Chip Manufacturer | SAMSUNG |
K1C6416B2D
CRE (CONTROL REGISTER ENABLE)
UtRAM2
The control registers store the values for the various modes to make UtRAM suitable for a various applications. The configuration
register values are written via Address pins. In an asynchronous WRITE, the values are latched into the configuration register on
the rising edge of ADV, CS, or WE, whichever occurs first; LB and UB are “Don’t Care.” For reads, address inputs other than
A[19:18] are “Don’t Care,” and register bits 15:0 are output as data (ADV HIGH) on A[15:0]. Immediately after performing a config-
uration register READ or WRITE operation, reading the memory array is highly recommended.
Bus Configuration Register
The BCR defines how the device interacts with the system memory bus. The BCR is accessed with CRE HIGH and A[19:18] =
10b, or through the register access software sequence with A = 0001h on the third cycle.
A19~A18
RS
A15
OM
A14
IL
A13~A11
LC
A10
WP
A8
WC
A5~A4
DS
A3
BW
A2~A0
BL
Register Select
A19
0
1
0
A18
0
0
1
RS
RCR
BCR
DIDR
A15
0
1
Operating Mode
OM
Synch.
Asynch (default)
A14
0
1
Initial Latency
IL
Variable (default)
Fixed
A13
0
0
0
0
1
1
1
1
Latency Count
A12
0
0
1
1
0
0
1
1
A11
0
1
0
1
0
1
0
1
LC
0
1
2
3 (default)
4
5
6
7
Wait Polarity
A10
0
1
WP
Active Low
Active High (default)
Wait Config.
A8
0
1
WC
at data
1 CLK prior
(default)
A5
0
0
1
1
Driver Strength
A4
0
1
0
1
DS
Full Drive
1/2 Drive
(default)
1/4 Drive
Reserved
Burst Wrap
A3
0
1
BW
Wrap
No Wrap
(default)
A2
0
0
0
1
1
Burst Length
A1
0
1
1
0
1
A0
1
0
1
0
1
BL
4 word
8 word
16 word
32 word
Continuous
(default)
1. A6, A7, A9, A16, A17, A20, A21 are reserved and should be ’1’
2. The registers are set automatically to default value.
3. Refresh command will be denied during continuous operation. CS low should not be longer than tBC(max. 2.5us)
Refresh Configuration Register
The refresh configuration register (RCR) defines how the device performs its self refresh. Altering the refresh parameters can
reduce current consumption during standby mode. The RCR is accessed with CRE HIGH and A[19:18] = 00b; or through the reg-
ister access software sequence with A = 0000h on the third cycle.
A19~A18
RS
A7
PAGE
A4
DPD
A2~A0
PAR
Register Select
A19
0
1
0
Page
A7
0
1
Deep Power Down
A4
0
1
Partial Refresh
A2
0
0
0
0
1
1
1
1
A18
0
0
1
RS
RCR
BCR
DIDR
PAGE
Disable
Enable(default)
DPD
Enable
Disable (default)
A1
0
0
1
1
0
0
1
1
A0
0
1
0
1
0
1
0
1
PAR
Full Array (default)
Bottom 1/2 Array
Bottom 1/4 Array
Bottom 1/8 Array
None of Array
Bottom 1/2 Array
Bottom 1/4 Array
Bottom 1/8 Array
1. A3, A5, A6, A8~A15, A16, A17, A20, A21 are reserved and should be ’1’
2. The registers are set automatically to default value.
-5-
Revision 3.0
Sep 2007
