K1C6416B2D-BI70
| Model | K1C6416B2D-BI70 |
| Description | Memory IC, 4MX16, CMOS, PBGA54 |
| PDF file | Total 50 pages (File size: 1M) |
| Chip Manufacturer | SAMSUNG |
K1C6416B2D
Asynchronous WRITE Followed by Burst READ
(CRE=V
IL
)
t
CLK
CLK
V
IH
V
IL
t
WC
A[21:0]
V
IH
V
IL
V
IH
V
IL
V
IH
LB/UB
V
IL
V
IH
V
IL
V
IH
V
IL
t
AS
WE
V
IH
V
IL
V
OH
V
OL
t
ACLK
DQ[15:0]
V
IH
IN/OUT
V
IL
High-Z
UtRAM2
t
WC
Valid Address
t
SP
t
HD
Valid Address
Valid Address
t
AVS
ADV
t
AW
t
WR
t
SP
t
HD
t
AHCR
t
VP
t
VS
t
BW
t
SP
t
HD
t
CVS
t
CW
t
AS
t
CBPH
t
CSP
CS
Note 2
t
OHZ
OE
t
WC
t
WP
t
WPH
t
SP
t
HD
t
CSW
t
CSW
t
BOE
High-Z
WAIT
t
KOH
V
OH
V
OL
Data
t
DH
Data
t
DW
High-Z
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Don’t Care
Undefined
Notes:
1. Non-default BCR settings for asynchronous WRITE followed by burst READ: Fixed or variable latency; latency code two (three clocks); WAIT
active LOW; WAIT asserted during delay.
2. When transitioning between asynchronous and variable-latency burst operations, CS must go HIGH. CS can stay LOW when transitioning to fixed-
latency burst READs. A refresh opportunity must be provided every tCSM. A refresh opportunity is satisfied by either of the following two condi-
tions: a) clocked CS HIGH, or b) CS HIGH for longer than 15ns.
3. Don’t care must be in V
IL
or V
IH
.
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Revision 3.0
Sep 2007
