G1-300P-85-2.0
Model | G1-300P-85-2.0 |
Description | Processor Series Low Power Integrated x86 Solution |
PDF file | Total 247 pages (File size: 4M) |
Chip Manufacturer | NSC |
Geode™ GX1 Processor Series
Integrated Functions
(Continued)
SDRAM Refresh Cycle
ory controller always precedes the refresh cycle with a
PRE command to all banks.
Page Miss
miss cycle. In order to program the new row address, a
PRE command must be issued followed by an ACT com-
mand.
SDCLK
CS#
RAS#
CAS#
WE#
MA[10]
Figure 4-7. Auto Refresh Cycle
SDCLK
COMMAND
PRE
NOP
NOP
ACT
NOP
NOP
R/W
NOP
tRP
tRCD
ADDRESS
BA
ROW
COL
Figure 4-8. READ/WRT Command to a New Row Address
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