G1-300P-85-2.0
| Model | G1-300P-85-2.0 |
| Description | Processor Series Low Power Integrated x86 Solution |
| PDF file | Total 247 pages (File size: 4M) |
| Chip Manufacturer | NSC |
Geode™ GX1 Processor Series
Integrated Functions
(Continued)
Table 4-44. PCI Configuration Registers
Bit
Index 00h-01h
31:0
VID (RO)
Name
Description
Vendor Identification Register (RO)
Default Value = 1078h
Vendor Identification register (Read Only):
The combination of this value and the device ID uniquely
identifies any PCI device. The Vendor ID is the ID given to National Semiconductor Corporation by the
PCI SIG.
Device Identification Register (RO)
Default Value = 0001h
Index 02h-03h
31:0
DIR (RO)
Device Identification register (Read Only):
This value along with the vendor ID uniquely identifies any
PCI device.
PCI Command Register (R/W)
Default Value = 0007h
Index 04h-05h
15:10
9
RSVD
FBE
Reserved:
Set to 0.
Fast Back-to-Back Enable (RO):
As a master, the GX1 processor does not support this function.
This bit returns 0.
8
7
SERR
WAT
SERR# Enable:
This is used as an output enable gate for the SERR# driver.
Wait Cycle Control:
GX1 processor does not do address/data stepping.
This bit is always set to 0.
6
PE
Parity Error Response:
0 = GX1 processor ignores parity errors on the PCI bus.
1 = GX1 processor checks for parity errors.
VGA Palette Snoop:
GX1 processor does not support this function.
This bit is always set to 0.
5
VPS
4
MS
Memory Write and Invalidate Enable:
As a master, the GX1 processor does not support this function.
This bit is always set to 0.
3
SPC
Special Cycles:
GX1 processor does not respond to special cycles on the PCI bus.
This bit is always set to 0.
2
BM
Bus Master:
0 = GX1 processor does not perform master cycles on the PCI bus.
1 = GX1 processor can act as a bus master on the PCI bus.
Memory Space:
GX1 processor will always respond to memory cycles on the PCI bus.
This bit is always set to 1.
1
MS
0
IOS
I/O Space:
GX1 processor will not respond to I/O accesses from the PCI bus.
This bit is always set to 1.
Index 06h-07h
15
DPE
PCI Device Status Register (RO, R/W Clear)
Detected Parity Error:
When a parity error is detected, this bit is set to 1.
This bit can be cleared to 0 by writing a 1 to it.
Default Value = 0280h
14
13
SSE
RMA
Signaled System Error:
This bit is set whenever SERR# is driven active.
Received Master Abort:
This bit is set whenever a master abort cycle occurs. A master abort will occur
whenever a PCI cycle is not claimed except for special cycles.
This bit can be cleared to 0 by writing a 1 to it.
12
RTA
Received Target Abort:
This bit is set whenever a target abort is received while the GX1 processor is
master of the cycle.
This bit can be cleared to 0 by writing a 1 to it.
11
STA
Signaled Target Abort:
This bit is set whenever the GX1 processor signals a target abort. A target abort
is signaled when an address parity occurs for an address that hits in the GX1 processor’s address space.
This bit can be cleared to 0 by writing a 1 to it.
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Revision 1.0
