G1-300P-85-2.0
| Model | G1-300P-85-2.0 |
| Description | Processor Series Low Power Integrated x86 Solution |
| PDF file | Total 247 pages (File size: 4M) |
| Chip Manufacturer | NSC |
Geode™ GX1 Processor Series
Processor Programming
(Continued)
Task State Segments Descriptors
The CPU enables rapid task switching using JMP and
CALL instructions that refer to Task State Segment (TSS)
descriptors. During a switch, the complete task state of the
current task is stored in its TSS, and the task state of the
requested task is loaded from its TSS. The TSSs are
defined through special segment descriptors and gates.
The
Task Register (TR)
holds 16-bit descriptors that con-
tain the base address and segment limit for each task state
segment. The TR is loaded and stored via the LTR and
STR instructions, respectively. The TR can be accessed
only during protected mode and can be loaded when the
privilege level is 0 (most privileged). When the TR is
loaded, the TR selector field indexes a TSS descriptor that
must reside in the Global Descriptor Table (GDT).
Only the 16-bit selector of a TSS descriptor in the TR is
accessible. The BASE, TSS LIMIT and ACCESS RIGHT
fields are program invisible.
During task switching, the processor saves the current
CPU state in the TSS before starting a new task. The TSS
can be either a 386/486-type 32-bit TSS (see Table 3-26) or a
286-type 16-bit TSS (see Table 3-27).
Task Gate Descriptors.
A task gate descriptor provides
controlled access to the descriptor for a task switch. The
DPL of the task gate is used to control access. The selec-
tor’s RPL and the CPL of the procedure must be a higher
level (numerically less) than the DPL of the descriptor. The
RPL in the task gate is not used.
The I/O Map Base Address field in the 32-bit TSS points to
an I/O permission bit map that often follows the TSS at
location +68h.
Table 3-26. 32-Bit Task State Segment (TSS) Table
1
31
I/O Map Base Address
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
EDI
ESI
EBP
ESP
EBX
EDX
ECX
EAX
EFLAGS
EIP
CR3
0
0
0
0
1.
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SS for CPL = 2
SS for CPL = 1
SS for CPL = 0
Back Link (Old TSS Selector)
ESP for CPL = 2
ESP for CPL = 1
ESP for CPL = 0
16 15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
T
+64h
+60h
+5Ch
+58h
+54h
+50h
+4Ch
+48h
+44h
+40h
+3Ch
+38h
+34h
+30h
+2Ch
+28h
+24h
+20h
+1Ch
+18h
+14h
+10h
+Ch
+8h
+4h
+0h
Selector for Task’s LDT
GS
FS
DS
SS
CS
ES
0 = Reserved
Revision 1.0
75
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