G1-300P-85-2.0
| Model | G1-300P-85-2.0 |
| Description | Processor Series Low Power Integrated x86 Solution |
| PDF file | Total 247 pages (File size: 4M) |
| Chip Manufacturer | NSC |
Geode™ GX1 Processor Series
2.0
Signal Definitions
This section describes the external interface of the Geode GX1 processor. Figure 2-1 shows the signals organized by their
functional interface groups (internal test and electrical pins are not shown).
System
Interface
Signals
SYSCLK
CLKMODE[2:0]
RESET
INTR
IRQ13
SMI#
SUSP#
SUSPA#
SERIALP
AD[31:0]
C/BE[3:0]#
PAR
FRAME#
IRDY#
TRDY#
STOP#
LOCK#
DEVSEL#
PERR#
SERR#
REQ[2:0]#
GNT[2:0]#
Geode™
GX1
Processor
MD[63:0]
MA[12:0]
BA[1:0]
RASA#, RASB#
CASA#, CASB#
CS[3:0]#
WEA#, WEB#
DQM[7:0]
CKEA, CKEB
SDCLK[3:0]
SDCLK_IN
SDCLK_OUT
PCLK
VID_CLK
DCLK
CRT_HSYNC
CRT_VSYNC
FP_HSYNC
FP_VSYNC
ENA_DISP
VID_RDY
VID_VAL
VID_DATA[7:0]
PIXEL[17:0]
Memory
Controller
Interface
Signals
PCI
Interface
Signals
Video
Interface
Signals
Figure 2-1. Functional Block Diagram
Revision 1.0
19
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