G1-300P-85-2.0
| Model | G1-300P-85-2.0 |
| Description | Processor Series Low Power Integrated x86 Solution |
| PDF file | Total 247 pages (File size: 4M) |
| Chip Manufacturer | NSC |
Geode™ GX1 Processor Series
Processor Programming
(Continued)
Table 3-35. SMM Memory Space Header Description
Name
DR7
EFLAGS
CR0
Current IP
Next IP
CS Selector
CS Descriptor
N
V
X
Description
Debug Register 7:
The contents of Debug Register 7.
Extended Flags Register:
The contents of Extended Flags Register.
Control Register 0:
The contents of Control Register 0.
Current Instruction Pointer:
The address of the instruction executed prior to servicing SMM
interrupt.
Next Instruction Pointer:
The address of the next instruction that will be executed after exiting
SMM.
Code Segment Selector:
Code segment register selector for the current code segment.
Code Segment Descriptor:
Encoded descriptor bits for the current code segment.
Nested SMI Status:
Flag that determines whether an SMI occurred during SMM (i.e., nested).
SoftVGA SMI Status:
SMI was generated by an access to VGA region.
External SMI Status:
If = 1: SMI generated by external SMI# pin.
If = 0: SMI internally generated by Internal Bus Interface Unit.
M
H
S
Memory or I/O Access:
0 = I/O access; 1 = Memory access.
Halt Status:
Indicates that the processor was in a halt or shutdown prior to servicing the SMM
interrupt.
Software SMM Entry Indicator:
If = 1: Current SMM is the result of an SMINT instruction.
If = 0: Current SMM is not the result of an SMINT instruction.
P
REP INSx/OUTSx Indicator:
1
If = 1: Current instruction has a REP prefix.
If = 0: Current instruction does not have a REP prefix.
I
IN, INSx, OUT, or OUTSx Indicator:
If = 1: Current instruction performed is an I/O WRITE.
If = 0: Current instruction performed is an I/O READ.
C
CS Writable:
Code Segment Writable
If = 1: CS is writable.
If = 0: CS is not writable.
I/O Data Size
Indicates size of data for the trapped I/O cycle:
01h = BYTE
03h = WORD
0Fh = DWORD
I/O Address
I/O or Memory Data
Restored ESI or EDI
Memory Address
1.
Processor port used for the trapped I/O cycle
Data associated with the trapped I/O or memory cycles
Restored ESI or EDI Value:
Used when it is necessary to repeat a REP OUTSx or REP INSx
instruction when one of the I/O cycles caused an SMI# trap.
Physical address of the operation that caused the SMI
Size
4 Bytes
4 Bytes
4 Bytes
4 Bytes
4 Bytes
2 Bytes
8 Bytes
1 Bit
1 Bit
1 Bit
1 Bit
1 Bit
1 Bit
1 Bit
1 Bit
1 Bit
2 Bytes
2 Bytes
4 Bytes
4 Bytes
4 Bytes
INSx = INS, INSB, INSW or INSD instruction.
OUTSx = OUTS, OUTSB, OUTSW and OUTSD instruction.
www.national.com
86
Revision 1.0
