G1-300P-85-2.0
| Model | G1-300P-85-2.0 |
| Description | Processor Series Low Power Integrated x86 Solution |
| PDF file | Total 247 pages (File size: 4M) |
| Chip Manufacturer | NSC |
Geode™ GX1 Processor Series
Electrical Specifications
(Continued)
Table 6-16. PCI Interface Signals (Refer to Figures 6-7 and 6-8)
Symbol
t
VAL1
t
VAL2
t
ON
t
OFF
t
SU1
t
SU2
t
H
1.
2.
Parameter
Delay Time, SYSCLK to Signal Valid for Bused Signals
Delay Time, SYSCLK to Signal Valid for GNT#
1, 2
Delay Time, Float to Active
Delay Time, Active to Float
Input Setup Time for Bused Signals
Input Setup Time for REQ#
Input Hold Time to SYSCLK
7
6
0
Min
2
2
2
28
Max
11
9
Unit
ns
ns
ns
ns
ns
ns
ns
GNT# and REQ# are point-to-point signals. All other PCI interface signals are bused.
Refer to Chapter 4 of PCI Local Bus Specification, Revision 2.1, for more detailed information.
Maximum timings are improved over the PCI Local Bus Specification, Revision 2.1. This allows a PAL or some other
circuit to use a REQ/GNT pair to expand the number of REQ/GNT pairs available to the system.
SYSCLK
t
VAL1,2
OUTPUT
TRI-STATE®
OUTPUT
t
ON
t
OFF
Figure 6-7. Output Timing
SYSCLK
t
SU1,2
t
H
INPUT
Figure 6-8. Input Timing
Revision 1.0
201
www.national.com
