G1-300P-85-2.0
| Model | G1-300P-85-2.0 |
| Description | Processor Series Low Power Integrated x86 Solution |
| PDF file | Total 247 pages (File size: 4M) |
| Chip Manufacturer | NSC |
Geode™ GX1 Processor Series
Integrated Functions
(Continued)
Table 4-44. PCI Configuration Registers (Continued)
Bit
10:9
Name
DT
Description
Device Timing:
The GX1 processor performs medium DEVSEL# active for addresses that hit into the
GX1 processor address space. These two bits are always set to 01.
00 = Fast
01 = Medium
10 = Slow
11 = Reserved
8
DPD
Data Parity Detected:
This bit is set when all three conditions are met.
1) GX1 processor asserted PERR# or observed PERR# asserted;
2) GX1 processor is the master for the cycle in which the PERR# occurred; and
3) PE (bit 6 of Command register) is enabled.
This bit can be cleared to 0 by writing a 1 to it.
7
FBS
Fast Back-to-Back Capable:
As a target, the processor is capable of accepting Fast Back-to-Back trans-
actions.
This bit is always set to 1.
6:0
Index 08h
7:0
RID (RO)
RSVD
Reserved:
Set to 0.
Revision Identification Register (RO)
Default Value = 00h
Revision ID (Read Only):
This register contains the revision number of the GX1 design.
Class Code Register (RO)
Default Value = 060000h
Index 09h-0Bh
23:16
15:0
Index 0Ch
7:0
Index 0Dh
7:5
4:0
RSVD
LAT_TIMER
Reserved:
Set to 0.
CACHELINE
CLASS
RSVD (RO)
Class Code:
The class code register is used to identify the generic function of the device. The
GX1 processor is classified as a host bridge device (06).
Reserved (Read Only)
Cache Line Size Register (RO)
Default Value = 00h
Cache Line Size (Read Only):
The cache line size register specifies the system cache line size in units
of 32-bit words. This function is not supported in the GX1 processor.
Latency Timer Register (R/W)
Default Value = 00h
Latency Timer:
The latency timer as used in this implementation will prevent a system lockup resulting
from a slave that does not respond to the master. If the register value is set to 00h, the timer is disabled.
Otherwise, Timer represents the 5 MSBs of an 8-bit counter. The counter will reset on each valid data
transfer. If the counter expires before the next TRDY# is received active, then the slave is considered to
be incapable of responding, and the master will stop the transaction with a master abort and flag an
SERR# active. This would also keep the master from being retried forever by a slave device that contin-
ues to issue retries. In these cases, the master will also stop the cycle with a master abort.
Reserved
PCI Control Function 1 Register (R/W)
Default Value = 00h
Default Value = 00h
Index 0Eh-3Fh
Index 40h
7
6
RSVD
SW
Reserved:
Set to 0.
Single Write Mode:
GX1 as a PCI slave supports:
0 = Multiple PCI write cycles
1 = Single cycle write transfers on the PCI bus. The slave will perform a target disconnect with the first
data transferred.
5
SR
Single Read Mode:
GX1 as a PCI slave supports:
0 = Multiple PCI read cycles.
1 = Single cycle read transfers on the PCI bus. The slave will perform a target disconnect with the first
data transferred.
4
RXBNE
Force Retry when X-Bus Buffers are Not Empty:
GX1 as a PCI slave:
0 = Accepts the PCI cycle with data in the PCI master write buffers. The data in the PCI master write buff-
ers will not be affected or corrupted. The PCI master holds request active indicating the need to access
the PCI bus.
1 = Retries cycles if the PCI master X-Bus write buffers contain buffered data.
Revision 1.0
171
www.national.com
