G1-300P-85-2.0
| Model | G1-300P-85-2.0 |
| Description | Processor Series Low Power Integrated x86 Solution |
| PDF file | Total 247 pages (File size: 4M) |
| Chip Manufacturer | NSC |
Geode™ GX1 Processor Series
Processor Programming
(Continued)
3.7.9.1
CPU States Related to SMM and Suspend
Mode
The state diagram shown in Figure 3-12 illustrates the vari-
ous CPU states associated with SMM and Suspend mode.
While in the SMM service routine, the GX1 processor core
can enter Suspend mode either by (1) executing a halt
(HLT) instruction or (2) by asserting the SUSP# input.
During SMM operations and while in SUSP#-initiated Sus-
pend mode, an occurrence of either an NMI or INTR is
latched. (In order for INTR to be latched, the IF flag,
EFLAGS register bit 9, must be set.) The INTR or NMI is
serviced after exiting Suspend mode.
If Suspend mode is entered through a HLT instruction from
the operating system or application software, the reception
of an SMI# interrupt causes the CPU to exit Suspend mode
and enter SMM. If Suspend mode is entered through the
hardware (SUSP# = 0) while the operating system or appli-
cation software is active, the CPU latches one occurrence
of INTR, NMI, and SMI#.
Suspend Mode
(SUSPA# = 0)
HLT*
NMI or INTR
Interrupt Service
Routine
IRET*
NMI or INTR
SUSP# = 0
SUSP# = 1
RESET
OS/Application
Software
Suspend Mode
(SUSPA# = 0)
(INTR, NMI and SMI# latched)
SMI# = 0
SMI# = 0
SMINT*
RSM*
Non-SMM Operations
SMM Operations
SMM Service Routine
(SMI# = 0)
HLT*
Suspend Mode
(SUSPA# = 0)
IRET*
SUSP# = 0
Interrupt Service
Routine
Suspend Mode
(SUSPA# = 0)
*Instructions
(INTR and NMI latched)
Interrupt Service
Routine
SUSP# = 1
NMI or INTR
NMI or INTR
IRET*
Figure 3-12. SMM and Suspend Mode State Diagram
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