G1-300P-85-2.0
| Model | G1-300P-85-2.0 |
| Description | Processor Series Low Power Integrated x86 Solution |
| PDF file | Total 247 pages (File size: 4M) |
| Chip Manufacturer | NSC |
Geode™ GX1 Processor Series
Power Management
(Continued)
5.3
POWER MANAGEMENT REGISTERS
Note, however, the PM_BASE and PM_MASK registers
are accessed with the CPU_READ and CPU_WRITE
instructions. Refer to Section 4.1.6 “CPU_READ/
tion regarding these instructions.
Tables 5-2 and 5-3 give these register’s bit formats.
The GX1 processor contains the power management reg-
isters for the serial packet transmission control, the user-
defined power management address space, Suspend
Refresh, and SMI status for Suspend/Resume. These
registers are memory mapped (GX_BASE+8500h-8FFFh)
in the address space of the GX1 processor and are
described in the following sections. Refer to Section 4.1.2
ing these registers.
Table 5-1. Power Management Register Summary
GX_BASE+
Memory Offset
Type
Name/Function
Default
Value
Control and Status Registers
8500h-8503h
R/W
PM_STAT_SMI
PM SMI Status register: Contains System Management Mode (SMM) status infor-
mation used by SoftVGA.
8504h-8507h
R/W
PM_CNTRL_TEN
PM Serial Packet Control register: Sets the serial packet transmission frequency
and enables specific CPU events to be recorded in the serial packet.
8508h-850Bh
R/W
PM_CNTRL_CSTP
PM Clock Stop Control register: Enables the 3V Suspend Mode for the GX1 pro-
cessor.
850Ch-850Fh
R/W
PM_SER_PACK
PM Serial Packet register: Transmits the contents of the serial packet.
Programmable Address Region Registers
FFFFFF6Ch
R/W
PM_BASE
PM Base register: Contains the base address for the programmable memory
range decode. This register, in combination with the PM_MASK register, is used to
generate a memory range decode which sets bit 1 in the serial transmission
packet.
FFFFFF7Ch
R/W
PM_MASK
PM Mask register: The address mask for the PM_BASE register
00000000h
00000000h
xxxxxx00h
xxxxxx00h
xxxxxx00h
xxxxxx00h
Table 5-2. Power Management Control and Status Registers
Bit
Name
Description
PM_STAT_SMI Register (R/W)
Reserved:
These bits are not used. Do not write to these bits.
Reserved:
Set to 0.
SMI VGA Emulation Memory:
This bit is set high if a SMI was generated for VGA emulation in
response to a VGA memory access. An SMI can be generated on a memory access to one of three
regions in the A0000h to BFFFFh range as specified in the BC_XMAP_1 register. (See Table 4-9 on
SMI VGA Emulation I/O:
This bit is set high if a SMI was generated for VGA emulation in response
to an I/O access. An SMI can be generated on a I/O access to one of three regions in the 3B0h to
3DFh range as specified in the BC_XMAP_1 register. (See Table 4-9 on page 104)
SMI Pin:
When set high, this bit indicates that the SMI# input pin has been asserted to the
GX1 processor.
Default Value = xxxxxx00h
GX_BASE+8500h-8503h
31:8
7:3
2
RSVD
RSVD
SMI_MEM
1
SMI_IO
0
Note:
SMI_PIN
These bits are “sticky” bits and can only be cleared with a write of ‘1’ to the respective bit.
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