G1-300P-85-2.0
| Model | G1-300P-85-2.0 |
| Description | Processor Series Low Power Integrated x86 Solution |
| PDF file | Total 247 pages (File size: 4M) |
| Chip Manufacturer | NSC |
Geode™ GX1 Processor Series
Instruction Set
(Continued)
Table 8-27. Processor Core Instruction Set Summary (Continued)
Flags
Instruction
SUB
Integer Subtract
Register to Register
Register to Memory
Memory to Register
Immediate to Register/Memory
Immediate to Accumulator (short form)
SVDC
Save Segment Register and Descriptor
SVLDT
Save LDTR and Descriptor
SVTS
Save TSR and Descriptor
TEST
Test Bits
Register/Memory and Register
Immediate Data and Register/Memory
Immediate Data and Accumulator
VERR
Verify Read Access
To Register/Memory
VERW
Verify Write Access
To Register/Memory
WAIT
Wait Until FPU Not Busy
WBINVD
Write-Back and Invalidate Cache
WRMSR
Write to Model Specific Register
XADD
Exchange and Add
Register1, Register2
Memory, Register
XCHG
Exchange
Register/Memory with Register
Register with Accumulator
XLAT
Translate Byte
XOR
Boolean Exclusive OR
Register to Register
Register to Memory
Memory to Register
Immediate to Register/Memory
Immediate to Accumulator (short form)
3 [00dw] [11 reg r/m]
3 [000w] [mod reg r/m]
3 [001w] [mod reg r/m]
8 [00sw] [mod 110 r/m] ###
3 [010w] ###
0 -
-
-
x
x
u x
0
1
1
1
1
1
1
1
1
1
1
b
h
8[011w] [mod reg r/m]
9[0 reg]
D7
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
2
2
5
2
2
5
h
b,f
f,h
0F C[000w] [11 reg2 reg1]
0F C[000w] [mod reg r/m]
x
-
-
-
x
x
x
x
x
2
2
2
2
0F 00 [mod 101 r/m]
9B
0F 09
0F 30
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
x
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1
23
8
1
23
t
t
a
g,h,j,p
0F 00 [mod 100 r/m]
-
-
-
-
-
x
-
-
-
8
a
g,h,j,p
8 [010w] [mod reg r/m]
F [011w] [mod 000 r/m] ###
A [100w] ###
0
- -
-
x
x
u x
0
1
1
1
1
1
1
b
h
2 [10dw] [11 reg r/m]
2 [100w] [mod reg r/m]
2 [101w] [mod reg r/m]
8 [00sw] [mod 101 r/m] ###
2 [110w] ###
0F 78 [mod sreg3 r/m]
0F 7A [mod 000 r/m]
0F 7C [mod 000 r/m]
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
x
- -
-
x
x
x
x
x
1
1
1
1
1
20
20
21
1
1
1
1
1
20
20
21
s
s
s
s
s
s
b
h
Opcode
O D I T S Z A P C
F F F F F F F F F
Real
Mode
Prot’d
Mode
Real
Mode
Prot’d
Mode
Clock Count
(Reg/Cache Hit)
Issues
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