G1-300P-85-2.0
| Model | G1-300P-85-2.0 |
| Description | Processor Series Low Power Integrated x86 Solution |
| PDF file | Total 247 pages (File size: 4M) |
| Chip Manufacturer | NSC |
Geode™ GX1 Processor Series
Integrated Functions
(Continued)
4.7.8.2 PCI Write Transaction
A PCI write transaction is similar to a PCI read transaction,
consisting of an address phase and one or more data
phases. Since the master provides both address and data,
no turnaround cycle is required following the address
phase. The data phases work the same for both read and
write transactions. Figure 4-19 illustrates a write transac-
tion.
The address phase begins on clock 2 when FRAME# is
asserted. The first and second data phases complete with-
out delays. During data phase 3, the target inserts three
wait cycles by deasserting TRDY#.
For additional information refer to Chapter 3.3.2, Write
Transaction, of the PCI Local Bus Specification, Revision
2.1.
CLK
FRAME#
AD
ADDR
DATA-1
DATA-2
DATA-3
C/BE#
BUS CMD
BE#s-1
BE#s-2
BE#s-3
DATA TRANSFER
IRDY#
WAIT
DEVSEL#
WAIT
ADDR
PHASE
DATA
PHASE
DATA
PHASE
BUS TRANSACTION
DATA
PHASE
Figure 4-19. Basic Write Operation
Revision 1.0
175
WAIT
TRDY#
DATA TRANSFER
DATA TRANSFER
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