U1AFS600-1PQG208
| Model | U1AFS600-1PQG208 |
| Description | Field Programmable Gate Array, |
| PDF file | Total 334 pages (File size: 18M) |
| Chip Manufacturer | MICROSEMI |
Device Architecture
There are several popular ADC architectures, each with advantages and limitations. The analog-to-digital
converter in Fusion devices is a switched-capacitor Successive Approximation Register (SAR) ADC. It
supports 8-, 10-, and 12-bit modes of operation with a cumulative sample rate up to 600 k samples per
second (ksps). Built-in bandgap circuitry offers 1% internal voltage reference accuracy or an external
reference voltage can be used.
As shown in
a SAR ADC contains N capacitors with binary-weighted values.
Comparator
C
C/2
C/4
C / 2
N–2
C / 2
N–1
VIN
VREF
Figure 2-79 •
Example SAR ADC Architecture
To begin a conversion, all of the capacitors are quickly discharged. Then VIN is applied to all the
capacitors for a period of time (acquisition time) during which the capacitors are charged to a value very
close to VIN. Then all of the capacitors are switched to ground, and thus –VIN is applied across the
comparator. Now the conversion process begins. First, C is switched to VREF
.
Because of the binary
weighting of the capacitors, the voltage at the input of the comparator is then shown by
Voltage at input of comparator = –VIN + VREF / 2
EQ 11
If VIN is greater than VREF / 2, the output of the comparator is 1; otherwise, the comparator output is 0.
A register is clocked to retain this value as the MSB of the result. Next, if the MSB is 0, C is switched
back to ground; otherwise, it remains connected to VREF, and C / 2 is connected to VREF. The result at
the comparator input is now either –VIN + VREF / 4 or –VIN + 3 VREF / 4 (depending on the state of the
MSB), and the comparator output now indicates the value of the next most significant bit. This bit is
likewise registered, and the process continues for each subsequent bit until a conversion is completed.
The conversion process requires some acquisition time plus N + 1 ADC clock cycles to complete.
2- 10 0
R e visio n 2
