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Home > Data Sheet > U1AFS600-1PQG208
U1AFS600-1PQG208

U1AFS600-1PQG208

Model U1AFS600-1PQG208
Description Field Programmable Gate Array,
PDF file Total 334 pages (File size: 18M)
Chip Manufacturer MICROSEMI
Fusion Family of Mixed Signal FPGAs
Table 2-113 •
2.5 V LVCMOS High Slew
Commercial Temperature Range Conditions: T
J
= 70°C, Worst-Case VCC = 1.425 V,
Worst-Case VCCI = 2.3 V
Applicable to Pro I/Os
Drive
Strength
4 mA
Speed
Grade t
DOUT
Std.
–1
–2
8 mA
Std.
–1
–2
12 mA
Std.
–1
–2
16 mA
Std.
–1
–2
24 mA
Std.
–1
–2
0.60
0.51
0.45
0.60
0.51
0.45
0.66
0.56
0.49
0.66
0.56
0.49
0.66
0.56
0.49
t
DP
8.82
7.50
6.58
5.27
4.48
3.94
3.74
3.18
2.80
3.53
3.00
2.63
3.26
2.77
2.44
t
DIN
0.04
0.04
0.03
0.04
0.04
0.03
0.04
0.04
0.03
0.04
0.04
0.03
0.04
0.04
0.03
t
PY
1.51
1.29
1.13
1.51
1.29
1.13
1.51
1.29
1.13
1.51
1.29
1.13
1.51
1.29
1.13
t
PYS
t
EOUT
1.66
1.41
1.24
1.66
1.41
1.24
1.66
1.41
1.24
1.66
1.41
1.24
1.66
1.41
1.24
0.43
0.36
0.32
0.43
0.36
0.32
0.43
0.36
0.32
0.43
0.36
0.32
0.43
0.36
0.32
t
ZL
8.13
6.92
6.07
5.27
4.48
3.93
3.81
3.24
2.85
3.59
3.06
2.68
3.32
2.83
2.48
t
ZH
8.82
7.50
6.58
5.27
4.48
3.94
3.49
2.97
2.61
3.12
2.65
2.33
2.48
2.11
1.85
t
LZ
2.72
2.31
2.03
3.10
2.64
2.32
3.37
2.86
2.51
3.42
2.91
2.56
3.49
2.97
2.61
t
HZ
2.29
1.95
1.71
3.03
2.58
2.26
3.49
2.97
2.61
3.62
3.08
2.71
4.11
3.49
3.07
t
ZLS
8.82
7.74
7.50
6.38
5.60
6.05
5.15
4.52
5.83
4.96
4.35
5.56
4.73
4.15
t
ZHS
9.40
8.25
7.51
6.38
5.61
5.73
4.87
4.28
5.35
4.55
4.00
4.72
4.01
3.52
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
10.37 11.05
Note:
For the derating values at specific junction temperature and voltage supply levels, refer to
Revision 2
2- 185
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