U1AFS600-1PQG208
| Model | U1AFS600-1PQG208 |
| Description | Field Programmable Gate Array, |
| PDF file | Total 334 pages (File size: 18M) |
| Chip Manufacturer | MICROSEMI |
Fusion Family of Mixed Signal FPGAs
Sequential Timing Characteristics
Table 2-2 •
Register Delays
Commercial Temperature Range Conditions: T
J
= 70°C, Worst-Case VCC = 1.425 V
Parameter
t
CLKQ
t
SUD
t
HD
t
SUE
t
HE
t
CLR2Q
t
PRE2Q
t
REMCLR
t
RECCLR
t
REMPRE
t
RECPRE
t
WCLR
t
WPRE
t
CKMPWH
t
CKMPWL
Description
Clock-to-Q of the Core Register
Data Setup Time for the Core Register
Data Hold Time for the Core Register
Enable Setup Time for the Core Register
Enable Hold Time for the Core Register
Asynchronous Clear-to-Q of the Core Register
Asynchronous Preset-to-Q of the Core Register
Asynchronous Clear Removal Time for the Core Register
Asynchronous Clear Recovery Time for the Core Register
Asynchronous Preset Removal Time for the Core Register
Asynchronous Preset Recovery Time for the Core Register
Asynchronous Clear Minimum Pulse Width for the Core Register
Asynchronous Preset Minimum Pulse Width for the Core Register
Clock Minimum Pulse Width High for the Core Register
Clock Minimum Pulse Width Low for the Core Register
–2
0.55
0.43
0.00
0.45
0.00
0.40
0.40
0.00
0.22
0.00
0.22
0.22
0.22
0.32
0.36
–1
0.63
0.49
0.00
0.52
0.00
0.45
0.45
0.00
0.25
0.00
0.25
0.25
0.25
0.37
0.41
Std.
0.74
0.57
0.00
0.61
0.00
0.53
0.53
0.00
0.30
0.00
0.30
0.30
0.30
0.43
0.48
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note:
For the derating values at specific junction temperature and voltage supply levels, refer to
Revision 2
2 -7
