U1AFS600-1PQG208
| Model | U1AFS600-1PQG208 |
| Description | Field Programmable Gate Array, |
| PDF file | Total 334 pages (File size: 18M) |
| Chip Manufacturer | MICROSEMI |
Fusion Family of Mixed Signal FPGAs
Real-Time Counter System
The RTC system enables Fusion devices to support standby and sleep modes of operation to reduce
power consumption in many applications.
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Sleep mode, typical 10 µA
Standby mode (RTC running), typical 3 mA with 20 MHz
RTC sub-block inside Analog Block (AB)
Voltage Regulator and Power System Monitor (VRPSM)
Crystal oscillator (XTLOSC); refer to the "Crystal Oscillator" section in the Fusion Clock
Resources chapter of the
for more detail.
Crystal clock; does not require instantiation in RTL
1.5 V voltage regulator; does not require instantiation in RTL
The RTC system is composed of five cores:
All cores are powered by 3.3 V supplies, so the RTC system is operational without a 1.5 V supply during
standby mode.
shows their connection.
3.3 V
AB
Real-Time Counter
RTCMATCH
VRPSM
VRPU
VRINITSTATE
RTCPSMMATCH
RTCPSMMATCH
FPGAGOOD
PUCORE
1.5 Voltage Regulator
External
Pass
Transistor
2N2222
PTBASE*
VREN*
VREN*
PTEM*
1.5 V
RTCCLK
PUB
RTCXTLSEL
RTCXTLMODE[1:0]
TRST*
XTLOSC
SELMODE
MODE[1:0]
FPGA_EN
2
XTL
Crystal Clock
XTL*
Power-Up/-Down
Toggle Control
Switch
External Pin
Internal Pin
RTC_MODE[1:0]
Can Be Route
to PLL
CLKOUT
XTAL1
XTAL2
Cores do not require any
RTL instantiation
Cores require RTL instantiation
1
Sub-block in cores does not
require additional RTL instantiation
Notes:
1. User is only required to instantiate the VRPSM macro if the user wishes to specify PUPO behavior of the voltage regulator
to be different from the default, or employ user logic to shut the voltage regulator off.
2. Signals are hardwired internally and do not exist in the macro core.
Figure 2-27 •
Real-Time Counter System (not all the signals are shown for the AB macro)
Revision 2
2- 33
