U1AFS600-1PQG208
| Model | U1AFS600-1PQG208 |
| Description | Field Programmable Gate Array, |
| PDF file | Total 334 pages (File size: 18M) |
| Chip Manufacturer | MICROSEMI |
Fusion Family of Mixed Signal FPGAs
IEEE 1532 Characteristics
JTAG timing delays do not include JTAG I/Os. To obtain complete JTAG timing, add I/O buffer delays to
the corresponding standard selected; refer to the I/O timing characteristics in the
for more details.
Timing Characteristics
Table 2-186 •
JTAG 1532
Commercial Temperature Range Conditions: T
J
= 70°C, Worst-Case VCC = 1.425 V
Parameter
t
DISU
t
DIHD
t
TMSSU
t
TMDHD
t
TCK2Q
t
RSTB2Q
F
TCKMAX
t
TRSTREM
t
TRSTREC
t
TRSTMPW
Description
Test Data Input Setup Time
Test Data Input Hold Time
Test Mode Select Setup Time
Test Mode Select Hold Time
Clock to Q (data out)
Reset to Q (data out)
TCK Maximum Frequency
ResetB Removal Time
ResetB Recovery Time
ResetB Minimum Pulse
–2
0.50
1.00
0.50
1.00
6.00
20.00
25.00
0.00
0.20
TBD
–1
0.57
1.13
0.57
1.13
6.80
22.67
22.00
0.00
0.23
TBD
Std.
0.67
1.33
0.67
1.33
8.00
26.67
19.00
0.00
0.27
TBD
Units
ns
ns
ns
ns
ns
ns
MHz
ns
ns
ns
Note:
For the derating values at specific junction temperature and voltage supply levels, refer to
Revision 2
2- 233
