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Home > Data Sheet > U1AFS600-1PQG208
U1AFS600-1PQG208

U1AFS600-1PQG208

Model U1AFS600-1PQG208
Description Field Programmable Gate Array,
PDF file Total 334 pages (File size: 18M)
Chip Manufacturer MICROSEMI
Device Architecture
Table 2-106 •
3.3 V LVTTL / 3.3 V LVCMOS Low Slew
Commercial Temperature Range Conditions: T
J
= 70°C, Worst-Case VCC = 1.425 V,
Worst-Case VCCI = 3.0 V
Applicable to Advanced I/Os
Drive
Strength
4 mA
Speed
Grade
Std.
–1
–2
8 mA
Std.
–1
–2
12 mA
Std.
–1
–2
16 mA
Std.
–1
–2
24 mA
Std.
–1
–2
t
DOUT
0.66
0.56
0.49
0.66
0.56
0.49
0.66
0.56
0.49
0.66
0.56
0.49
0.66
0.56
0.49
t
DP
10.26
8.72
7.66
7.27
6.19
5.43
5.58
4.75
4.17
5.21
4.43
3.89
4.85
4.13
3.62
t
DIN
0.04
0.04
0.03
0.04
0.04
0.03
0.04
0.04
0.03
0.04
0.04
0.03
0.04
0.04
0.03
t
PY
1.20
1.02
0.90
1.20
1.02
0.90
1.20
1.02
0.90
1.20
1.02
0.90
1.20
1.02
0.90
t
EOUT
0.43
0.36
0.32
0.43
0.36
0.32
0.43
0.36
0.32
0.43
0.36
0.32
0.43
0.36
0.32
t
ZL
10.45
8.89
7.80
7.41
6.30
5.53
5.68
4.84
4.24
5.30
4.51
3.96
4.94
4.20
3.69
t
ZH
8.90
7.57
6.64
6.28
5.35
4.69
4.87
4.14
3.64
4.56
3.88
3.41
4.54
3.87
3.39
t
LZ
2.64
2.25
1.98
2.98
2.54
2.23
3.21
2.73
2.39
3.26
2.77
2.43
3.32
2.82
2.48
t
HZ
2.46
2.09
1.83
3.04
2.59
2.27
3.42
2.91
2.55
3.51
2.99
2.62
3.88
3.30
2.90
t
ZLS
12.68
10.79
9.47
9.65
8.20
7.20
7.92
6.74
5.91
7.54
6.41
5.63
7.18
6.10
5.36
t
ZHS
11.13
9.47
8.31
8.52
7.25
6.36
7.11
6.05
5.31
6.80
5.79
5.08
6.78
5.77
5.06
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note:
For the derating values at specific junction temperature and voltage supply levels, refer to
2- 18 0
R e visio n 2
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