U1AFS600-1PQG208
| Model | U1AFS600-1PQG208 |
| Description | Field Programmable Gate Array, |
| PDF file | Total 334 pages (File size: 18M) |
| Chip Manufacturer | MICROSEMI |
Fusion Family of Mixed Signal FPGAs
LVPECL
Low-Voltage Positive Emitter-Coupled Logic (LVPECL) is another differential I/O standard. It requires
that one data bit be carried through two signal lines. Like LVDS, two pins are needed. It also requires
external resistor termination.
The full implementation of the LVDS transmitter and receiver is shown in an example in
The building blocks of the LVPECL transmitter–receiver are one transmitter macro, one receiver macro,
three board resistors at the transmitter end, and one resistor at the receiver end. The values for the three
driver resistors are different from those used in the LVDS implementation because the output standard
specifications are different.
Bourns Part Number: CAT16-PC4F12
OUTBUF_LVPECL
FPGA
P
100
Ω
ZO = 50
Ω
187 W
100
Ω
P
FPGA
+
–
N
INBUF_LVPECL
N
100
Ω
ZO = 50
Ω
Figure 2-134 •
LVPECL Circuit Diagram and Board-Level Implementation
Table 2-171 •
Minimum and Maximum DC Input and Output Levels
DC Parameter
VCCI
VOL
VOH
VIL, VIH
VODIFF
VOCM
VICM
VIDIFF
Description
Supply Voltage
Output Low Voltage
Output High Voltage
Input Low, Input High Voltages
Differential Output Voltage
Output Common Mode Voltage
Input Common Mode Voltage
Input Differential Voltage
0.96
1.8
0
0.625
1.762
1.01
300
Min.
3.0
1.27
2.11
3.3
0.97
1.98
2.57
1.06
1.92
0
0.625
1.762
1.01
300
Max.
Min.
3.3
1.43
2.28
3.6
0.97
1.98
2.57
1.30
2.13
0
0.625
1.762
1.01
300
Max.
Min.
3.6
1.57
2.41
3.9
0.97
1.98
2.57
Max.
Units
V
V
V
V
V
V
V
mV
Table 2-172 •
AC Waveforms, Measuring Points, and Capacitive Loads
Input Low (V)
1.64
Input High (V)
1.94
Measuring Point* (V)
Cross point
VREF (typ.) (V)
–
Note:
*Measuring point = Vtrip. See
for a complete table of trip points.
Timing Characteristics
Table 2-173 •
LVPECL
Commercial Temperature Range Conditions: T
J
= 70°C, Worst-Case VCC = 1.425 V,
Worst-Case VCCI = 3.0 V
Applicable to Pro I/Os
Speed Grade
Std.
–1
–2
t
DOUT
0.66
0.56
0.49
t
DP
2.14
1.82
1.60
t
DIN
0.04
0.04
0.03
t
PY
1.63
1.39
1.22
Units
ns
ns
ns
Note:
For the derating values at specific junction temperature and voltage supply levels, refer to
Revision 2
2- 213
