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Home > Data Sheet > U1AFS600-1PQG208
U1AFS600-1PQG208

U1AFS600-1PQG208

Model U1AFS600-1PQG208
Description Field Programmable Gate Array,
PDF file Total 334 pages (File size: 18M)
Chip Manufacturer MICROSEMI
Fusion Family of Mixed Signal FPGAs
Table 2-83 •
Fusion Pro I/O Supported Standards and Corresponding VREF and VTT Voltages
I/O Standard
LVTTL/LVCMOS 3.3 V
LVCMOS 2.5 V
LVCMOS 2.5 V / 5.0 V
Input
LVCMOS 1.8 V
LVCMOS 1.5 V
PCI 3.3 V
PCI-X 3.3 V
GTL+ 3.3 V
GTL+ 2.5 V
GTL 3.3 V
GTL 2.5 V
HSTL Class I
HSTL Class II
SSTL3 Class I
SSTL3 Class II
SSTL2 Class I
SSTL2 Class II
LVDS, BLVDS, M-LVDS
LVPECL
Input/Output Supply
Voltage (VCCI_TYP)
3.30 V
2.50 V
2.50 V
1.80 V
1.50 V
3.30 V
3.30 V
3.30 V
2.50 V
3.30 V
2.50 V
1.50 V
1.50 V
3.30 V
3.30 V
2.50 V
2.50 V
2.50 V
3.30 V
Input Reference Voltage
(VREF_TYP)
1.00 V
1.00 V
0.80 V
0.80 V
0.75 V
0.75 V
1.50 V
1.50 V
1.25 V
1.25 V
Board Termination Voltage
(VTT_TYP)
1.50 V
1.50 V
1.20 V
1.20 V
0.75 V
0.75 V
1.50 V
1.50 V
1.25 V
1.25 V
Revision 2
2- 157
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