U1AFS600-1PQG208
| Model | U1AFS600-1PQG208 |
| Description | Field Programmable Gate Array, |
| PDF file | Total 334 pages (File size: 18M) |
| Chip Manufacturer | MICROSEMI |
Device Architecture
SSTL3 Class II
Stub-Speed Terminated Logic for 3.3 V memory bus standard (JESD8-8). Fusion devices support Class
II. This provides a differential amplifier input buffer and a push-pull output buffer.
Table 2-165 •
Minimum and Maximum DC Input and Output Levels
SSTL3 Class II
Drive Strength
21 mA
Notes:
1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.
2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is
larger when operating outside recommended ranges.
3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
4. Currents are measured at 85°C junction temperature.
VIL
Min.
V
–0.3
Max.
V
VIH
Min.
V
Max.
V
3.6
VOL
Max.
V
0.5
VOH
Min.
V
VCCI – 0.9
IOL IOH
mA mA
21
21
IOSL
Max.
mA
3
109
IOSH
Max.
mA
3
103
IIL
1
IIH
2
µA
4
µA
4
10
10
VREF – 0.2 VREF + 0.2
SSTL3
Class II
Test Point
25
VTT
25
30 pF
Figure 2-131 •
AC Loading
Table 2-166 •
AC Waveforms, Measuring Points, and Capacitive Loads
Input Low (V)
VREF – 0.2
Input High (V)
VREF + 0.2
Measuring Point* (V)
1.5
VREF (typ.) (V)
1.5
VTT (typ.) (V)
1.485
C
LOAD
(pF)
30
Note:
*Measuring point = Vtrip. See
for a complete table of trip points.
Timing Characteristics
Table 2-167 •
SSTL3- Class II
Commercial Temperature Range Conditions: T
J
= 70°C, Worst-Case VCC = 1.425 V,
Worst-Case VCCI = 3.0 V, VREF = 1.5 V
Speed
Grade
Std.
–1
–2
t
DOUT
0.66
0.56
0.49
t
DP
2.07
1.76
1.54
t
DIN
0.04
0.04
0.03
t
PY
1.25
1.06
0.93
t
EOUT
0.43
0.36
0.32
t
ZL
2.10
1.79
1.57
t
ZH
1.67
1.42
1.25
t
LZ
t
HZ
t
ZLS
4.34
3.69
3.24
t
ZHS
3.91
3.32
2.92
Units
ns
ns
ns
Note:
For the derating values at specific junction temperature and voltage supply levels, refer to
2- 21 0
R e visio n 2
