U1AFS600-1PQG208
| Model | U1AFS600-1PQG208 |
| Description | Field Programmable Gate Array, |
| PDF file | Total 334 pages (File size: 18M) |
| Chip Manufacturer | MICROSEMI |
Fusion Family of Mixed Signal FPGAs
Clocking Resources
The Fusion family has a robust collection of clocking peripherals, as shown in the block diagram in
These on-chip resources enable the creation, manipulation, and distribution of many clock
signals. The Fusion integrated RC oscillator produces a 100 MHz clock source with no external
components. For systems requiring more precise clock signals, the Fusion family supports an on-chip
crystal oscillator circuit. The integrated PLLs in each Fusion device can use the RC oscillator, crystal
oscillator, or another on-chip clock signal as a source. These PLLs offer a variety of capabilities to modify
the clock source (multiply, divide, synchronize, advance, or delay). Utilizing the CCC found in the popular
ProASIC3 family, Fusion incorporates six CCC blocks. The CCCs allow access to Fusion global and local
clock distribution nets, as described in the
Off-Chip
On-Chip
GNDOSC
VCCOSC
100 MHz
RC Oscillator
Clock Out to FPGA Core through CCC
XTAL1
XTAL2
External
External
Crystal or
RC
Crystal Oscillator
Xtal Clock
Clock I/Os
From FPGA Core
Figure 2-16 •
Fusion Clocking Options
GLINT
To Core
CLKOUT
PLL/
CCC
GLA
GLC
NGMUX
Revision 2
2- 19
