U1AFS600-1PQG208
| Model | U1AFS600-1PQG208 |
| Description | Field Programmable Gate Array, |
| PDF file | Total 334 pages (File size: 18M) |
| Chip Manufacturer | MICROSEMI |
Fusion Family of Mixed Signal FPGAs
No-Glitch MUX (NGMUX)
Positioned downstream from the PLL/CCC blocks, the NGMUX provides a special switching sequence
between two asynchronous clock domains that prevents generating any unwanted narrow clock pulses.
The NGMUX is used to switch the source of a global between three different clock sources. Allowable
inputs are either two PLL/CCC outputs or a PLL/CCC output and a regular net, as shown in
The GLMUXCFG[1:0] configuration bits determine the source of the CLK inputs (i.e., internal signal or
GLC). These are set by SmartGen during design but can also be changed by dynamically reconfiguring
the PLL. The GLMUXSEL[1:0] bits control which clock source is passed through the NGMUX to the global
network (GL). See
Crystal Oscillator
RC Oscillator
W I/O Ring
CCC/PLL
GLMUXCFG[1:0]
GLINT
PLL/
CCC
Clock I/Os
From FPGA Core
GLA
GLC
NGMUX
To Clock Rib Driver
GL
PWR UP
GLMUXSEL[1:0]
Figure 2-24 •
NGMUX
Table 2-13 •
NGMUX Configuration and Selection Table
GLMUXCFG[1:0]
00
GLMUXSEL[1:0]
X
X
01
X
X
0
1
0
1
Selected Input
Signal
GLA
GLC
GLA
GLINT
2-to-1 GLMUX
MUX Type
2-to-1 GLMUX
Revision 2
2- 31
