U1AFS600-1PQG208
| Model | U1AFS600-1PQG208 |
| Description | Field Programmable Gate Array, |
| PDF file | Total 334 pages (File size: 18M) |
| Chip Manufacturer | MICROSEMI |
Fusion Family of Mixed Signal FPGAs
Detailed I/O DC Characteristics
Table 2-95 •
Input Capacitance
Symbol
C
IN
C
INCLK
Definition
Input capacitance
Input capacitance on the clock pin
Conditions
VIN = 0, f = 1.0 MHz
VIN = 0, f = 1.0 MHz
Min.
Max.
8
8
Units
pF
pF
Table 2-96 •
I/O Output Buffer Maximum Resistances
1
Standard
Applicable to Pro I/O Banks
3.3 V LVTTL / 3.3 V LVCMOS
4 mA
8 mA
12 mA
16 mA
24 mA
2.5 V LVCMOS
4 mA
8 mA
12 mA
16 mA
24 mA
1.8 V LVCMOS
2 mA
4 mA
6 mA
8 mA
12 mA
16 mA
1.5 V LVCMOS
2 mA
4 mA
6 mA
8 mA
12 mA
3.3 V PCI/PCI-X
3.3 V GTL
2.5 V GTL
3.3 V GTL+
2.5 V GTL+
Notes:
1. These maximum values are provided for informational reasons only. Minimum output buffer resistance values depend
on VCC, drive strength selection, temperature, and process. For board design considerations and detailed output buffer
resistances, use the corresponding IBIS models located on the Microsemi SoC Products Group website:
2. R
(PULL-DOWN-MAX)
= VOLspec / I
OLspec
3. R
(PULL-UP-MAX)
= (VCCImax – VOHspec) / IOHspec
Drive Strength
R
PULL-DOWN
(ohms)
2
100
50
25
17
11
100
50
25
20
11
200
100
50
50
20
20
200
100
67
33
33
25
11
14
12
15
R
PULL-UP
(ohms)
3
300
150
75
50
33
200
100
50
40
22
225
112
56
56
22
22
224
112
75
37
37
75
–
–
–
–
Per PCI/PCI-X specification
25 mA
25 mA
35 mA
33 mA
Revision 2
2- 171
