T1022NXE7MQA
| Model | T1022NXE7MQA |
| Description | 32-BIT, 1200MHz, RISC PROCESSOR, PBGA780 |
| PDF file | Total 197 pages (File size: 1M) |
| Chip Manufacturer | PHILIPS |
Electrical characteristics
SDHC_CLK
external clock
VM
VM
t
NIIVKH
VM
t
NIIXKH
VM
SDHC_DAT/CMD inputs
SDHC_DAT/CMD outputs
t
NIKHOV
t
NIKHOX
VM = Midpoint voltage (OV
DD
/2)
Figure 45. eSDHC data and command input/output timing diagram referenced to clock
This table provides the eSDHC AC timing specifications for SDR50 mode (EV
DD
/CV
DD
= 1.8V).
Table 82. eSDHC AC timing (SDR50)
2
Parameter
SDHC_CLK clock frequency:
SDHC_CLK duty cycle
SDHC_CLK clock rise and fall times
Skew between SDHC_CLK_SYNC_OUT and SDHC_CLK
Input setup times: SDHC_CMD, SDHC_DATx to
SDHC_CLK_SYNC_IN
Input hold times: SDHC_CMD, SDHC_DATx to
SDHC_CLK_SYNC_IN
Output hold time: SDHC_CLK to SDHC_CMD, SDHC_DATx valid,
SDHC_DATx_DIR, SDHC_CMD_DIR
Output delay time: SDHC_CLK to SDHC_CMD, SDHC_DATx valid,
SDHC_DATx_DIR, SDHC_CMD_DIR
Notes:
1. C
CARD
≤ 10 pF, (1 card), and C
L
= C
BUS
+ C
HOST
+ C
CARD
≤ 30 pF.
2. For recommended operating conditions, see
t
SCKR/
t
SCKF
—
t
NIIVKH
t
NIIXKH
t
NIKHOX
t
NIKHOV
-0.1
2.1
0.9
2.4
-
0.1
-
-
-
6.3
ns
ns
ns
ns
ns
—
Symbol
f
SCK
47
-
Min
53
2
Max
100
%
ns
1
Unit
MHz
Notes
This figure provides the eSDHC clock input timing diagram for SDR50 mode.
QorIQ T1042, T1022 Data Sheet, Rev. 2, 06/2015
116
Freescale Semiconductor, Inc.
