T1022NXE7MQA
| Model | T1022NXE7MQA |
| Description | 32-BIT, 1200MHz, RISC PROCESSOR, PBGA780 |
| PDF file | Total 197 pages (File size: 1M) |
| Chip Manufacturer | PHILIPS |
Hardware design considerations
NOTE
Only SMT capacitors should be used to minimize inductance.
Connections from all capacitors to power and ground should be
done with multiple vias to further reduce inductance.
1. The board should have at least 1 x 0.1-uF SMT ceramic chip capacitor placed as
close as possible to each supply ball of the device. Where the board has blind vias,
these capacitors should be placed directly below the chip supply and ground
connections. Where the board does not have blind vias, these capacitors should be
placed in a ring around the device as close to the supply and ground connections as
possible.
2. Between the device and any SerDes voltage regulator there should be a lower bulk
capacitor for example a 10-uF, low ESR SMT tantalum or ceramic and a higher bulk
capacitor for example a 100uF - 300-uF low ESR SMT tantalum or ceramic
capacitor.
4.5 Connection recommendations
The following is a list of connection recommendations:
• To ensure reliable operation, it is highly recommended to connect unused inputs to
an appropriate signal level. Unless otherwise noted in this document, all unused
active low inputs should be tied to V
DD
, OnV
DD
, DV
DD
, GnV
DD
, EV
DD
, CV
DD
and
LnV
DD
as required. All unused active high inputs should be connected to GND. All
NC (no-connect) signals must remain unconnected. Power and ground connections
must be made to all external V
DD
, OnV
DD
, DV
DD
, GnV
DD
, LnV
DD
, EV
DD
, CV
DD
and GND pins of the device.
• The TEST_SEL_B pin must be pulled to O1V
DD
through a 100-ohm to 1k-ohm
resistor for T1042 and tied to ground for 2 core T1022.
• The chip has temperature diodes on the microprocessor that can be used in
conjunction with other system temperature monitoring devices (such as Analog
Devices, ADT7461A
™
). If a temperature diode monitoring device is not connected,
these pins may be connected to test points or grounded.
4.5.1 Legacy JTAG configuration signals
Correct operation of the JTAG interface requires configuration of a group of system
control pins as demonstrated in
Care must be taken to ensure that these pins
are maintained at a valid deasserted state under normal operating conditions as most have
asynchronous behavior and spurious assertion will give unpredictable results.
QorIQ T1042, T1022 Data Sheet, Rev. 2, 06/2015
176
Freescale Semiconductor, Inc.
