T1022NXE7MQA
| Model | T1022NXE7MQA |
| Description | 32-BIT, 1200MHz, RISC PROCESSOR, PBGA780 |
| PDF file | Total 197 pages (File size: 1M) |
| Chip Manufacturer | PHILIPS |
Electrical characteristics
Table 29. DDR4 and DDR3L SDRAM interface output AC timing specifications
8
(continued)
Parameter
1600 MT/s data rate
1300 MT/s data rate
1200 MT/s data rate
1000 MT/s data rate
MDQS preamble
MDQS postamble
t
DDKHMP
t
DDKHME
Symbol
1
400
500
550
600
900 x t
MCK
400 x t
MCK
Min
-
-
-
-
-
600 x t
MCK
ps
ps
Max
Unit
5
5
5, 6
5, 6
-
-
Notes
1. The symbols used for timing specifications follow the pattern of t
(first two letters of functional block)(signal)(state) (reference)(state)
for
inputs and t
(first two letters of functional block)(reference)(state)(signal)(state)
for outputs. Output hold time can be read as DDR timing (DD)
from the rising or falling edge of the reference clock (KH or KL) until the output went invalid (AX or DX). For example, t
DDKHAS
symbolizes DDR timing (DD) for the time t
MCK
memory clock reference (K) goes from the high (H) state until outputs (A) are
setup (S) or output valid time. Also, t
DDKLDX
symbolizes DDR timing (DD) for the time t
MCK
memory clock reference (K) goes
low (L) until data outputs (D) are invalid (X) or data output hold time.
2. All MCK/MCK_B and MDQS/MDQS_B referenced measurements are made from the crossing of the two signals.
3. ADDR/CMD/CNTL includes all DDR SDRAM output signals except MCK/MCK_B, MCS_B, and MDQ/MECC/MDM/MDQS.
4. Note that t
DDKHMH
follows the symbol conventions described in note 1. For example, t
DDKHMH
describes the DDR timing
(DD) from the rising edge of the MCK[n] clock (KH) until the MDQS signal is valid (MH). t
DDKHMH
can be modified through
control of the MDQS override bits (called WR_DATA_DELAY) in the TIMING_CFG_2 register. This is typically set to the
same delay as in DDR_SDRAM_CLK_CNTL[CLK_ADJUST]. The timing parameters listed in the table assume that these two
parameters have been set to the same adjustment value. See the chip reference manual for a description and explanation of
the timing modifications enabled by the use of these bits.
5. Available eye for data (MDQ), ECC (MECC), and data mask (MDM) outputs at the pin of the processor. Memory controller
will center the strobe (MDQS) in the available data eye at the DRAM (end point) during the initialization.
6. DDR3L only
7. Note that it is required to program the start value of the MDQS adjust for write leveling.
8. For recommended operating conditions, see
NOTE
For the ADDR/CMD/CNTL setup and hold specifications in
it is assumed that the clock control register is set to
adjust the memory clocks by �½ applied cycle.
This figure shows the DDR4 and DDR3L SDRAM interface output timing for the MCK
to MDQS skew measurement (t
DDKHMH
).
QorIQ T1042, T1022 Data Sheet, Rev. 2, 06/2015
Freescale Semiconductor, Inc.
73
