T1022NXE7MQA
| Model | T1022NXE7MQA |
| Description | 32-BIT, 1200MHz, RISC PROCESSOR, PBGA780 |
| PDF file | Total 197 pages (File size: 1M) |
| Chip Manufacturer | PHILIPS |
Hardware design considerations
Note that both S1V
DD
and X1V
DD
must remain powered.
If any of the PLLs are un-used, the corresponding AVDD_SD1_PLL1 must be connected
to X1V
DD
through a zero ohm resistor (instead of filter circuit shown in
The following unused pins must be left unconnected:
• SD1_TX[7:0]_P
• SD1_TX[7:0]_N
The following unused pins must be connected to S1GND:
• SD1_REF_CLK[1:2]_P, SD1_REF_CLK[1:2]_N (If entire SerDes unused)
It is recommended for the following unused pins to be connected to S1GND:
• SD1_RX[7:0]_P
• SD1_RX[7:0]_N
In the RCW configuration field SRDS_PLL_PD_S1, the respective bits for each unused
PLL must be set to power it down. A module is disabled when both its PLLs are turned
off.
Unused lanes must be powered down through the SRDSx Lane m General Control
Register 0 (SRDSxLNmGCR0) as follows:
•
•
•
•
SRDSxLNmGCR0[RRST] = 0
SRDSxLNmGCR0[TRST] = 0
SRDSxLNmGCR0[RX_PD] = 1
SRDSxLNmGCR0[TX_PD] = 1
Note that in the case where the SerDes pins are connected to slots , it is acceptable to
have these pins unterminated when unused.
4.5.4 USB controller connections
This section details the hardware connections required for the USB controllers.
4.5.4.1
USB divider network
This figure shows the required divider network for the VBUS interface for the chip.
Additional requirements for the external components are:
• Both resistors require 1% accuracy and a current capability of up to 1 mA. They must
both have the same temperature coefficient and accuracy.
QorIQ T1042, T1022 Data Sheet, Rev. 2, 06/2015
186
Freescale Semiconductor, Inc.
