T1022NXE7MQA
| Model | T1022NXE7MQA |
| Description | 32-BIT, 1200MHz, RISC PROCESSOR, PBGA780 |
| PDF file | Total 197 pages (File size: 1M) |
| Chip Manufacturer | PHILIPS |
Electrical characteristics
Table 2. Absolute maximum ratings
1
(continued)
Characteristic
Input voltage
DDR4 and DDR3L DRAM signals
DDR4 and DDR3L DRAM reference
Ethernet signals
MV
IN
D1_MV
REF
LV
IN
LV1
IN
MPIC, GPIO, system control and power
OV
IN
management, clocking, debug, IFC, DDRCLK
O1V
IN
supply, and JTAG I/O voltage
eSDHC signals
eSPI signals
DUART, I
2
C, DMA, TDM, QE, MPIC, DIU
SerDes signals
USB PHY Transceiver signals
EV
IN
CV
IN
DV
IN
S1V
IN
USB_HV
IN
USB_OV
IN
Storage temperature range
Notes:
1. Functional operating conditions are given in
Absolute maximum ratings are stress ratings only, and functional
operation at the maximums is not guaranteed. Stresses beyond those listed may affect device reliability or cause permanent
damage to the device.
2.
Caution:
MV
IN
must not exceed G1V
DD
by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during
power-on reset and power-down sequences.
3.
Caution:
OV
IN
must not exceed OV
DD
by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during
power-on reset and power-down sequences.
4.
Caution:
LV
IN
must not exceed LV
DD
by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during
power-on reset and power-down sequences.
5. (S,G,L,O,D,E,C)V
IN
, USBn_V
IN
_3P3, USBn_V
IN
_1P8 and Dn_MV
REF
may overshoot/undershoot to a voltage and for a
maximum duration as shown in
6.
Caution:
DV
IN
must not exceed DV
DD
by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during
power-on reset and power-down sequences.
7.
Caution:
EV
IN
must not exceed EV
DD
by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during
power-on reset and power-down sequences.
8.
Caution:
CV
IN
must not exceed CV
DD
by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during
power-on reset and power-down sequences.
9. Supply voltage specified at the voltage sense pin. Voltage input pins should be regulated to provide specified voltage at the
sense pin.
10. AVDD_PLAT, AVDD_CGA1, AVDD_CGA2 and AVDD_D1 are measured at the input to the filter (as shown in AN4825)
and not at the pin of the device.
T
STG
Symbol
Max Value
-0.3 to (G1V
DD
+
0.3)
-0.3 to (G1V
DD
/2+
0.3)
-0.3 to (LnV
DD
+
0.3)
-0.3 to (OnV
DD
+
0.3)
Unit
V
V
V
V
Notes
2
5
4, 5
3, 5
-0.3 to (EV
DD
+ 0.3) V
-0.3 to (CV
DD
+ 0.3) V
-0.3 to (DV
DD
+ 0.3) V
-0.4 to (S1V
DD
+
0.3)
-0.3 to (USB_HV
DD
+ 0.3)
V
V
7, 5
8, 5
5, 6
5
5
5
-
-0.3 to (USB_OV
DD
V
+ 0.3)
-55 to 150
°C
QorIQ T1042, T1022 Data Sheet, Rev. 2, 06/2015
48
Freescale Semiconductor, Inc.
