T1022NXE7MQA
| Model | T1022NXE7MQA |
| Description | 32-BIT, 1200MHz, RISC PROCESSOR, PBGA780 |
| PDF file | Total 197 pages (File size: 1M) |
| Chip Manufacturer | PHILIPS |
Hardware design considerations
4.1.5 Core complex PLL select
The clock frequency of each core cluster is determined by the binary value of the RCW
Configuration field Cn_PLL_SEL. These tables describe the selections available to each
core cluster, where each individual core cluster can select a frequency from their
respective tables.
NOTE
There is a restriction that requires that the frequency provided
to the e5500 core cluster after any dividers must always be
greater than half of the platform frequency. Special care must
be used when selecting the /2 outputs of a cluster PLL in which
this restriction is observed.
Table 133. Core cluster PLL select
Binary Value of Cn_PLL_SEL for n=1-4
0000
0001
0100
0101
All Others
CGA PLL1 /1
CGA PLL1 /2
CGA PLL2 /1
CGA PLL2 /2
Reserved
Core cluster ratio
4.1.6 DDR controller PLL ratios
The DDR memory controller operates asynchronous to the platform.
In asynchronous DDR mode, the DDR data rate to DDRCLK ratios supported are listed
in the following table. This ratio is determined by the binary value of the RCW
Configuration field MEM_PLL_RAT (bits 10-15).
The RCW Configuration field MEM_PLL_CFG (bits 8-9) must be set to
MEM_PLL_CFG = 0b00 for all valid DDR PLL reference clock frequencies supported
on this chip.
Table 134. DDR clock ratio
Binary value of MEM_PLL_RAT
00_1000
00_1010
00_1011
8:1
10:1
11:1
Table continues on the next page...
DDR data-rate:DDRCLK ratio
Maximum supported DDR data-rate
(MT/s)
1066
1333
1465
QorIQ T1042, T1022 Data Sheet, Rev. 2, 06/2015
164
Freescale Semiconductor, Inc.
