T1022NXE7MQA
| Model | T1022NXE7MQA |
| Description | 32-BIT, 1200MHz, RISC PROCESSOR, PBGA780 |
| PDF file | Total 197 pages (File size: 1M) |
| Chip Manufacturer | PHILIPS |
Electrical characteristics
T
CLK
SDHC_CLK
T
NIKHOV
SDHC_CMD/SDHC_CMD_DIR
SDHC_DAT/SDHC_DATn_DIR
output
T
NIKHOX
Figure 48. eSDHC SDR50 mode output AC timing diagram
This table provides the eSDHC AC timing specifications for DDR50/eMMC DDR mode
(EV
DD
/CV
DD
= 1.8V).
Table 83. eSDHC AC timing (DDR50/eMMC DDR)
3
Parameter
SDHC_CLK clock frequency
SDHC_CLK duty cycle
Skew between SDHC_CLK_SYNC_OUT and SDHC_CLK
SDHC_CLK clock rise and fall
times
Input setup times: SDHC_DATx
to SDHC_CLK_SYNC_IN
SD/SDIO DDR50 mode
eMMC DDR mode
SD/SDIO DDR50 mode
eMMC DDR mode
t
NDIXKH
t
NDKHOX
SD/SDIO DDR50 mode
eMMC DDR mode
—
—
t
SCKR
/
t
SCKF
t
NDIVKH
0.5
0.6
0.98
0.98
2.2
3.9
t
NDKHOV
—
5.7
6.3
t
NIIVKH
t
NIIXKH
t
NIKHOX
3.3
2.7
0.4
0.4
2.2
4.4
—
ns
—
—
ns
—
—
ns
—
ns
—
—
ns
—
—
ns
—
47
-0.1
—
Symbol
f
SCK
—
Min
50
50
53
0.1
4
2
—
ns
%
ns
ns
—
—
1
2
—
Max
Units
MHz
Notes
—
Input hold times: SDHC_DATx to SD/SDIO DDR50 mode
SDHC_CLK_SYNC_IN
eMMC DDR mode
Output hold time: SDHC_CLK to
SDHC_DATx valid,
SDHC_DATx_DIR
SD/SDIO DDR50 mode
eMMC DDR mode
Output delay time: SDHC_CLK to SD/SDIO DDR50 mode
SDHC_DATx valid,
eMMC DDR mode
SDHC_DATx_DIR
Input setup times: SDHC_CMD to SD/SDIO DDR50 mode
SDHC_CLK_SYNC_IN
eMMC DDR mode
Input hold times: SDHC_CMD to
SDHC_CLK_SYNC_IN
Output hold time: SDHC_CLK to
SDHC_CMD valid,
SDHC_CMD_DIR
SD/SDIO DDR50 mode
eMMC DDR mode
SD/SDIO DDR50 mode
eMMC DDR mode
Table continues on the next page...
QorIQ T1042, T1022 Data Sheet, Rev. 2, 06/2015
118
Freescale Semiconductor, Inc.
